drm/i915: Program EXT2 GC MAX registers

EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.

v2: Updated the 1.0 programming and aligned as per GLK, also added
GLK along with GEN10+ check, as per Ville's feedback.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553869756-4546-3-git-send-email-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379a521bcab0fc2913ff7a99bf5656e94967..341f03e00536ea921164fbd36c09dbbce92120dd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10144,6 +10144,7 @@ enum skl_power_gate {
 #define PREC_PAL_DATA(pipe)            _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
 #define PREC_PAL_GC_MAX(pipe, i)       _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
 #define PREC_PAL_EXT_GC_MAX(pipe, i)   _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i)  _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
 
 #define _PRE_CSC_GAMC_INDEX_A  0x4A484
 #define _PRE_CSC_GAMC_INDEX_B  0x4AC84

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index c7761591ba7c1620e8d105f94b2435acd2b5525e..f2907cfd116a84730b49a90e06a2a55f14cf113e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -526,6 +526,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+               /*
+                * Program the gc max 2 register to clamp values > 1.0.
+                * ToDo: Extend the ABI to be able to program values
+                * from 3.0 to 7.0
+                */
+               if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+               }
        } else {
                for (i = 0; i < lut_size; i++) {
                        u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -537,6 +548,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
                I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+               /*
+                * Program the gc max 2 register to clamp values > 1.0.
+                * ToDo: Extend the ABI to be able to program values
+                * from 3.0 to 7.0
+                */
+               if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+                       I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+               }
        }
 
        /*