drm/i915: cache number of MOCS entries

Instead of checking the gen number every time we need to know the max
number of entries, just save it into the table struct so we don't need
extra branches throughout the code. This will be useful for Ice Lake
that has 64 rather than 62 defined entries. Ice Lake changes will be
added in a follow up.

v2: make size and n_entries `unsigned int` and introduce changes as a
    pre-work for the Ice Lake changes (Tvrtko)

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tomasz Lis <tomasz.lis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190124000604.18861-7-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index e5f0e9da258c28353027d1d1c7e2d59cae4a7762..6e293f91a10cff8119a3606fef52324d43c2ae9a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -32,7 +32,8 @@ struct drm_i915_mocs_entry {
 };
 
 struct drm_i915_mocs_table {
-       u32 size;
+       unsigned int size;
+       unsigned int n_entries;
        const struct drm_i915_mocs_entry *table;
 };
 
@@ -144,10 +145,12 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
        if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
            IS_ICELAKE(dev_priv)) {
                table->size  = ARRAY_SIZE(skylake_mocs_table);
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
                table->table = skylake_mocs_table;
                result = true;
        } else if (IS_GEN9_LP(dev_priv)) {
                table->size  = ARRAY_SIZE(broxton_mocs_table);
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
                table->table = broxton_mocs_table;
                result = true;
        } else {
@@ -219,8 +222,6 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
        if (!get_mocs_settings(dev_priv, &table))
                return;
 
-       GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);
-
        /* Set unused values to PTE */
        unused_value = table.table[I915_MOCS_PTE].control_value;
 
@@ -231,7 +232,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
        }
 
        /* All remaining entries are also unused */
-       for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
+       for (; index < table.n_entries; index++)
                I915_WRITE(mocs_register(engine->id, index), unused_value);
 }
 
@@ -253,17 +254,17 @@ static int emit_mocs_control_table(struct i915_request *rq,
        u32 unused_value;
        u32 *cs;
 
-       if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+       if (GEM_WARN_ON(table->size > table->n_entries))
                return -ENODEV;
 
        /* Set unused values to PTE */
        unused_value = table->table[I915_MOCS_PTE].control_value;
 
-       cs = intel_ring_begin(rq, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
+       cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
-       *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
+       *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries);
 
        for (index = 0; index < table->size; index++) {
                u32 value = get_entry_control(table, index);
@@ -273,7 +274,7 @@ static int emit_mocs_control_table(struct i915_request *rq,
        }
 
        /* All remaining entries are also unused */
-       for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
+       for (; index < table->n_entries; index++) {
                *cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
                *cs++ = unused_value;
        }
@@ -322,17 +323,17 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
        unsigned int i;
        u32 *cs;
 
-       if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+       if (GEM_WARN_ON(table->size > table->n_entries))
                return -ENODEV;
 
        /* Set unused values to PTE */
        unused_value = table->table[I915_MOCS_PTE].l3cc_value;
 
-       cs = intel_ring_begin(rq, 2 + GEN9_NUM_MOCS_ENTRIES);
+       cs = intel_ring_begin(rq, 2 + table->n_entries);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
-       *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
+       *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2);
 
        for (i = 0; i < table->size / 2; i++) {
                u16 low = get_entry_l3cc(table, 2 * i);
@@ -352,7 +353,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
        }
 
        /* All remaining entries are also unused */
-       for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
+       for (; i < table->n_entries / 2; i++) {
                *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
                *cs++ = l3cc_combine(table, unused_value, unused_value);
        }
@@ -407,7 +408,7 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
        }
 
        /* All remaining entries are also unused */
-       for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
+       for (; i < table.n_entries / 2; i++)
                I915_WRITE(GEN9_LNCFCMOCS(i),
                           l3cc_combine(&table, unused_value, unused_value));
 }