--- /dev/null
+From 960e1ef3c5b2d69a4a5a6984b6408d65221dd86c Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Sat, 23 Jun 2012 04:14:55 +0000
+Subject: [PATCH 06/81] MIPS: BCM63XX: Fix USB IRQ definitions for 6328
+
+OHCI/EHCI are in the high (second) word. Not currently used by any
+driver.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -602,8 +602,8 @@ enum bcm63xx_irq {
+ #define BCM_6328_ENET0_IRQ 0
+ #define BCM_6328_ENET1_IRQ 0
+ #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
+-#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
+-#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
++#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
++#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
+ #define BCM_6328_PCMCIA_IRQ 0
+ #define BCM_6328_ENET0_RXDMA_IRQ 0
+ #define BCM_6328_ENET0_TXDMA_IRQ 0
--- /dev/null
+From 21bb8141c205ae48d331787debb6b272add90ac7 Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Sat, 23 Jun 2012 04:14:54 +0000
+Subject: [PATCH 05/81] MIPS: BCM63XX: Add register definitions for USBD
+ dependencies
+
+The USB 2.0 device depends on some functionality in other blocks, such
+as GPIO and USBH. Add those register definitions here.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 6 +++---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 8 ++++++++
+ 2 files changed, 11 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -184,9 +184,9 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_SPI_BASE (0xdeadbeef)
+ #define BCM_6328_UDC0_BASE (0xdeadbeef)
+ #define BCM_6328_USBDMA_BASE (0xdeadbeef)
+-#define BCM_6328_OHCI0_BASE (0xdeadbeef)
++#define BCM_6328_OHCI0_BASE (0xb0002600)
+ #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
+-#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
++#define BCM_6328_USBH_PRIV_BASE (0xb0002700)
+ #define BCM_6328_MPI_BASE (0xdeadbeef)
+ #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
+ #define BCM_6328_PCIE_BASE (0xb0e40000)
+@@ -199,7 +199,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_ENETDMAC_BASE (0xb000da00)
+ #define BCM_6328_ENETDMAS_BASE (0xb000dc00)
+ #define BCM_6328_ENETSW_BASE (0xb0e00000)
+-#define BCM_6328_EHCI0_BASE (0x10002500)
++#define BCM_6328_EHCI0_BASE (0xb0002500)
+ #define BCM_6328_SDRAM_BASE (0xdeadbeef)
+ #define BCM_6328_MEMC_BASE (0xdeadbeef)
+ #define BCM_6328_DDR_BASE (0xb0003000)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -543,6 +543,12 @@
+ #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
+
+
++#define GPIO_PINMUX_OTHR_REG 0x24
++#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
++#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
++#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
++#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
++
+ #define GPIO_BASEMODE_6368_REG 0x38
+ #define GPIO_BASEMODE_6368_UART2 0x1
+ #define GPIO_BASEMODE_6368_GPIO 0x0
+@@ -770,6 +776,8 @@
+ #define USBH_PRIV_SWAP_6358_REG 0x0
+ #define USBH_PRIV_SWAP_6368_REG 0x1c
+
++#define USBH_PRIV_SWAP_USBD_SHIFT 6
++#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
+ #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
+ #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
+ #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
+#define BCM_6328_HSSPI_BASE (0xb0001000)
#define BCM_6328_UDC0_BASE (0xdeadbeef)
#define BCM_6328_USBDMA_BASE (0xdeadbeef)
- #define BCM_6328_OHCI0_BASE (0xdeadbeef)
+ #define BCM_6328_OHCI0_BASE (0xb0002600)
@@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6328_ENET1_IRQ 0
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
+#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
- #define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
- #define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
+ #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
+ #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
#define BCM_6328_PCMCIA_IRQ 0
@@ -640,6 +652,7 @@ enum bcm63xx_irq {
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1231,4 +1231,51 @@
+@@ -1239,4 +1239,51 @@
#define PCIE_DEVICE_OFFSET 0x8000
#define SOFTRESET_6368_SPI_MASK (1 << 0)
#define SOFTRESET_6368_MPI_MASK (1 << 3)
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
-@@ -1174,6 +1227,12 @@
+@@ -1182,6 +1235,12 @@
#define SERDES_PCIE_EN (1 << 0)
#define SERDES_PCIE_EXD_EN (1 << 15)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1223,7 +1223,8 @@
+@@ -1231,7 +1231,8 @@
/*************************************************************************
* _REG relative to RSET_MISC
*************************************************************************/
#endif /* ! BCM63XX_DEV_ENET_H_ */
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -803,10 +803,60 @@
+@@ -809,10 +809,60 @@
* _REG relative to RSET_ENETSW
*************************************************************************/
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -832,6 +832,19 @@
+@@ -838,6 +838,19 @@
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
return -ENODEV;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -608,6 +608,7 @@
+@@ -614,6 +614,7 @@
#define GPIO_STRAPBUS_REG 0x40
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
#define STRAPBUS_6368_BOOT_SEL_NAND 0
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
-@@ -1300,6 +1301,7 @@
+@@ -1308,6 +1309,7 @@
#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
#define MISC_STRAPBUS_6328_REG 0x240
return spi_register_board_info(bcm63xx_spi_flash_info,
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1296,6 +1296,7 @@
+@@ -1304,6 +1304,7 @@
#define MISC_STRAPBUS_6362_REG 0x14
#define STRAPBUS_6362_FCVO_SHIFT 1
#endif
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1215,6 +1215,22 @@
+@@ -1223,6 +1223,22 @@
#define SPI_6358_MSG_TAIL 0x709
#define SPI_6358_RX_TAIL 0x70B