bcm53xx: use upstream SPI controller fix

This just moves patch to use 0xx prefix and includes maintainer's s-o-b.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit 9b385b24967a53e88c31aee04ba629d276c4e69d)

diff --git a/target/linux/bcm53xx/patches-4.14/081-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch b/target/linux/bcm53xx/patches-4.14/081-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch
new file mode 100644 (file)
index 0000000..91b06b1
--- /dev/null
+++ b/target/linux/bcm53xx/patches-4.14/081-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch
@@ -0,0 +1,44 @@
+From 940ec770c295682993d1cccce3081fd7c74fece8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Oct 2018 09:42:17 +0200
+Subject: [PATCH] spi: bcm-qspi: switch back to reading flash using smaller
+ chunks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixing/optimizing bcm_qspi_bspi_read() performance introduced two
+changes:
+1) It added a loop to read all requested data using multiple BSPI ops.
+2) It bumped max size of a single BSPI block request from 256 to 512 B.
+
+The later change resulted in occasional BSPI timeouts causing a
+regression.
+
+For some unknown reason hardware doesn't always handle reads as expected
+when using 512 B chunks. In such cases it may happen that BSPI returns
+amount of requested bytes without the last 1-3 ones. It provides the
+remaining bytes later but doesn't raise an interrupt until another LR
+start.
+
+Switching back to 256 B reads fixes that problem and regression.
+
+Fixes: 345309fa7c0c ("spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Cc: stable@vger.kernel.org
+---
+ drivers/spi/spi-bcm-qspi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-bcm-qspi.c
++++ b/drivers/spi/spi-bcm-qspi.c
+@@ -88,7 +88,7 @@
+ #define BSPI_BPP_MODE_SELECT_MASK             BIT(8)
+ #define BSPI_BPP_ADDR_SELECT_MASK             BIT(16)
+ 
+-#define BSPI_READ_LENGTH                      512
++#define BSPI_READ_LENGTH                      256
+ 
+ /* MSPI register offsets */
+ #define MSPI_SPCR0_LSB                                0x000

diff --git a/target/linux/bcm53xx/patches-4.14/180-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch b/target/linux/bcm53xx/patches-4.14/180-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch
deleted file mode 100644 (file)
index 4b30565..0000000
--- a/target/linux/bcm53xx/patches-4.14/180-spi-bcm-qspi-switch-back-to-reading-flash-using-smal.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 11 Oct 2018 09:07:31 +0200
-Subject: [PATCH FIX] spi: bcm-qspi: switch back to reading flash using smaller
- chunks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Fixing/optimizing bcm_qspi_bspi_read() performance introduced two
-changes:
-1) It added a loop to read all requested data using multiple BSPI ops.
-2) It bumped max size of a single BSPI block request from 256 to 512 B.
-
-The later change resulted in occasional BSPI timeouts causing a
-regression.
-
-For some unknown reason hardware doesn't always handle reads as expected
-when using 512 B chunks. In such cases it may happen that BSPI returns
-amount of requested bytes without the last 1-3 ones. It provides the
-remaining bytes later but doesn't raise an interrupt until another LR
-start.
-
-Switching back to 256 B reads fixes that problem and regression.
-
-Fixes: 345309fa7c0c ("spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Cc: stable@vger.kernel.org # 4.11+
----
- drivers/spi/spi-bcm-qspi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/spi/spi-bcm-qspi.c
-+++ b/drivers/spi/spi-bcm-qspi.c
-@@ -88,7 +88,7 @@
- #define BSPI_BPP_MODE_SELECT_MASK             BIT(8)
- #define BSPI_BPP_ADDR_SELECT_MASK             BIT(16)
- 
--#define BSPI_READ_LENGTH                      512
-+#define BSPI_READ_LENGTH                      256
- 
- /* MSPI register offsets */
- #define MSPI_SPCR0_LSB                                0x000