drm/amd/powerplay: add raven support in smumgr. (v2)
authorRex Zhu <Rex.Zhu@amd.com>
Mon, 6 Mar 2017 11:10:08 +0000 (19:10 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 24 May 2017 21:41:51 +0000 (17:41 -0400)
smumgr provides the interface for interacting with the
smu firmware which handles power management.

v2: squash in updates (Alex)

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
new file mode 100644 (file)
index 0000000..9a01493
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RAVEN_INC_H
+#define RAVEN_INC_H
+
+
+#include "asic_reg/raven1/MP/mp_10_0_default.h"
+#include "asic_reg/raven1/MP/mp_10_0_offset.h"
+#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h"
+
+#include "asic_reg/raven1/NBIO/nbio_7_0_default.h"
+#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h"
+#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h"
+
+#include "asic_reg/raven1/THM/thm_10_0_default.h"
+#include "asic_reg/raven1/THM/thm_10_0_offset.h"
+#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h"
+
+
+#define ixDDI_PHY_GEN_STATUS                       0x3FCE8
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
new file mode 100644 (file)
index 0000000..65149c7
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RAVEN_PP_SMC_H
+#define RAVEN_PP_SMC_H
+
+#pragma pack(push, 1)
+
+#define PPSMC_Result_OK                    0x1
+#define PPSMC_Result_Failed                0xFF
+#define PPSMC_Result_UnknownCmd            0xFE
+#define PPSMC_Result_CmdRejectedPrereq     0xFD
+#define PPSMC_Result_CmdRejectedBusy       0xFC
+
+#define PPSMC_MSG_TestMessage                   0x1
+#define PPSMC_MSG_GetSmuVersion                 0x2
+#define PPSMC_MSG_GetDriverIfVersion            0x3
+#define PPSMC_MSG_EnableGfxOff                  0x7
+#define PPSMC_MSG_DisableGfxOff                 0x8
+#define PPSMC_MSG_PowerDownIspByTile            0x9
+#define PPSMC_MSG_PowerUpIspByTile              0xA
+#define PPSMC_MSG_PowerDownVcn                  0xB
+#define PPSMC_MSG_PowerUpVcn                    0xC
+#define PPSMC_MSG_PowerDownSdma                 0xD
+#define PPSMC_MSG_PowerUpSdma                   0xE
+#define PPSMC_MSG_SetHardMinIspclkByFreq        0xF
+#define PPSMC_MSG_SetHardMinVcn                 0x10
+#define PPSMC_MSG_SetMinDisplayClock            0x11
+#define PPSMC_MSG_SetHardMinFclkByFreq          0x12
+#define PPSMC_MSG_SetAllowFclkSwitch            0x13
+#define PPSMC_MSG_SetGfxMinActiveFreq           0x14
+#define PPSMC_MSG_ActiveProcessNotify           0x15
+#define PPSMC_MSG_SetCustomPolicy               0x16
+#define PPSMC_MSG_SetVideoFps                   0x17
+#define PPSMC_MSG_SetDisplayCount               0x18
+#define PPSMC_MSG_QueryPowerLimit               0x19
+#define PPSMC_MSG_SetDriverDramAddrHigh         0x1A
+#define PPSMC_MSG_SetDriverDramAddrLow          0x1B
+#define PPSMC_MSG_TransferTableSmu2Dram         0x1C
+#define PPSMC_MSG_TransferTableDram2Smu         0x1D
+#define PPSMC_MSG_ControlGfxRM                  0x1E
+#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
+#define PPSMC_MSG_SetHardMinDcefclkByFreq       0x20
+#define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
+#define PPSMC_MSG_SetMinVddcrSocVoltage         0x22
+
+
+#define PPSMC_Message_Count                     0x23
+
+typedef uint16_t PPSMC_Result;
+typedef int      PPSMC_Msg;
+
+
+#pragma pack(pop)
+
+#endif
index 37f41217b8a03da86704c3d99c2f2544e2d1f219..976e942ec69433f10c32dd29aee4617974a349c3 100644 (file)
@@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
 extern const struct pp_smumgr_func fiji_smu_funcs;
 extern const struct pp_smumgr_func polaris10_smu_funcs;
 extern const struct pp_smumgr_func vega10_smu_funcs;
+extern const struct pp_smumgr_func rv_smu_funcs;
 
 enum AVFS_BTC_STATUS {
        AVFS_BTC_BOOT = 0,
index 68b01b594e11fe2b6c5cefed9620c1f69891b719..1703bbefbfd52fb5d97537542b5cbb2e2cc914c8 100644 (file)
@@ -4,7 +4,7 @@
 
 SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
          polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
-         smu7_smumgr.o iceland_smc.o vega10_smumgr.o
+         smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
 
 AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
new file mode 100644 (file)
index 0000000..6b6b755
--- /dev/null
@@ -0,0 +1,352 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "smumgr.h"
+#include "rv_inc.h"
+#include "pp_soc15.h"
+#include "rv_smumgr.h"
+#include "ppatomctrl.h"
+#include "rv_ppsmc.h"
+#include "smu10_driver_if.h"
+#include "smu10.h"
+#include "ppatomctrl.h"
+#include "pp_debug.h"
+#include "smu_ucode_xfer_vi.h"
+#include "smu7_smumgr.h"
+
+#define VOLTAGE_SCALE 4
+
+#define BUFFER_SIZE                 80000
+#define MAX_STRING_SIZE             15
+#define BUFFER_SIZETWO              131072
+
+#define MP0_Public                  0x03800000
+#define MP0_SRAM                    0x03900000
+#define MP1_Public                  0x03b00000
+#define MP1_SRAM                    0x03c00004
+
+#define smnMP1_FIRMWARE_FLAGS       0x3010028
+
+
+bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
+{
+       uint32_t mp1_fw_flags, reg;
+
+       reg = soc15_get_register_offset(NBIF_HWID, 0,
+                       mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
+
+       cgs_write_register(smumgr->device, reg,
+                       (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
+
+       reg = soc15_get_register_offset(NBIF_HWID, 0,
+                       mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
+
+       mp1_fw_flags = cgs_read_register(smumgr->device, reg);
+
+       if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
+               return true;
+
+       return false;
+}
+
+static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr)
+{
+       uint32_t reg;
+
+       if (!rv_is_smc_ram_running(smumgr))
+               return -EINVAL;
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+
+       smum_wait_for_register_unequal(smumgr, reg,
+                       0, MP1_C2PMSG_90__CONTENT_MASK);
+
+       return cgs_read_register(smumgr->device, reg);
+}
+
+int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
+               uint16_t msg)
+{
+       uint32_t reg;
+
+       if (!rv_is_smc_ram_running(smumgr))
+               return -EINVAL;
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
+       cgs_write_register(smumgr->device, reg, msg);
+
+       return 0;
+}
+
+int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
+{
+       uint32_t reg;
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+
+       *arg = cgs_read_register(smumgr->device, reg);
+
+       return 0;
+}
+
+int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+{
+       uint32_t reg;
+
+       rv_wait_for_response(smumgr);
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+       cgs_write_register(smumgr->device, reg, 0);
+
+       rv_send_msg_to_smc_without_waiting(smumgr, msg);
+
+       PP_ASSERT_WITH_CODE(rv_wait_for_response(smumgr) == 1,
+                       "Failed to send Message.",
+                       return -EINVAL);
+
+       return 0;
+}
+
+
+int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+               uint16_t msg, uint32_t parameter)
+{
+       uint32_t reg;
+
+       rv_wait_for_response(smumgr);
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+       cgs_write_register(smumgr->device, reg, 0);
+
+       reg = soc15_get_register_offset(MP1_HWID, 0,
+                       mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+       cgs_write_register(smumgr->device, reg, parameter);
+
+       rv_send_msg_to_smc_without_waiting(smumgr, msg);
+
+       PP_ASSERT_WITH_CODE(rv_wait_for_response(smumgr) == 1,
+                       "Failed to send Message.",
+                       return -EINVAL);
+
+       return 0;
+}
+
+int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+               uint8_t *table, int16_t table_id)
+{
+       struct rv_smumgr *priv =
+                       (struct rv_smumgr *)(smumgr->backend);
+
+       PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+                       "Invalid SMU Table ID!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
+                       "Invalid SMU Table version!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
+                       "Invalid SMU Table Length!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_SetDriverDramAddrHigh,
+                       priv->smu_tables.entry[table_id].table_addr_high) == 0,
+                       "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_SetDriverDramAddrLow,
+                       priv->smu_tables.entry[table_id].table_addr_low) == 0,
+                       "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
+                       return -EINVAL;);
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_TransferTableSmu2Dram,
+                       priv->smu_tables.entry[table_id].table_id) == 0,
+                       "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
+                       return -EINVAL;);
+
+       memcpy(table, priv->smu_tables.entry[table_id].table,
+                       priv->smu_tables.entry[table_id].size);
+
+       return 0;
+}
+
+int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+               uint8_t *table, int16_t table_id)
+{
+       struct rv_smumgr *priv =
+                       (struct rv_smumgr *)(smumgr->backend);
+
+       PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+                       "Invalid SMU Table ID!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
+                       "Invalid SMU Table version!", return -EINVAL;);
+       PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
+                       "Invalid SMU Table Length!", return -EINVAL;);
+
+       memcpy(priv->smu_tables.entry[table_id].table, table,
+                       priv->smu_tables.entry[table_id].size);
+
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_SetDriverDramAddrHigh,
+                       priv->smu_tables.entry[table_id].table_addr_high) == 0,
+                       "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
+                       return -EINVAL;);
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_SetDriverDramAddrLow,
+                       priv->smu_tables.entry[table_id].table_addr_low) == 0,
+                       "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
+                       return -EINVAL;);
+       PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+                       PPSMC_MSG_TransferTableDram2Smu,
+                       priv->smu_tables.entry[table_id].table_id) == 0,
+                       "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
+                       return -EINVAL;);
+
+       return 0;
+}
+
+static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
+{
+       uint32_t smc_driver_if_version;
+
+       PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+                       PPSMC_MSG_GetDriverIfVersion),
+                       "Attempt to get SMC IF Version Number Failed!",
+                       return -EINVAL);
+       PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr,
+                       &smc_driver_if_version),
+                       "Attempt to read SMC IF Version Number Failed!",
+                       return -EINVAL);
+
+       if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION)
+               return -EINVAL;
+
+       return 0;
+}
+
+
+static int rv_smu_fini(struct pp_smumgr *smumgr)
+{
+       struct rv_smumgr *priv =
+                       (struct rv_smumgr *)(smumgr->backend);
+
+       if (priv) {
+               cgs_free_gpu_mem(smumgr->device,
+                               priv->smu_tables.entry[WMTABLE].handle);
+               cgs_free_gpu_mem(smumgr->device,
+                               priv->smu_tables.entry[CLOCKTABLE].handle);
+               kfree(smumgr->backend);
+               smumgr->backend = NULL;
+       }
+
+       return 0;
+}
+
+static int rv_start_smu(struct pp_smumgr *smumgr)
+{
+       if (rv_verify_smc_interface(smumgr))
+               return -EINVAL;
+
+       return 0;
+}
+
+static int rv_smu_init(struct pp_smumgr *smumgr)
+{
+       struct rv_smumgr *priv;
+       uint64_t mc_addr;
+       void *kaddr = NULL;
+       unsigned long handle;
+
+       priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
+
+       if (!priv)
+               return -ENOMEM;
+
+       smumgr->backend = priv;
+
+       /* allocate space for watermarks table */
+       smu_allocate_memory(smumgr->device,
+                       sizeof(Watermarks_t),
+                       CGS_GPU_MEM_TYPE__GART_CACHEABLE,
+                       PAGE_SIZE,
+                       &mc_addr,
+                       &kaddr,
+                       &handle);
+
+       PP_ASSERT_WITH_CODE(kaddr,
+                       "[rv_smu_init] Out of memory for wmtable.",
+                       kfree(smumgr->backend);
+                       smumgr->backend = NULL;
+                       return -EINVAL);
+
+       priv->smu_tables.entry[WMTABLE].version = 0x01;
+       priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
+       priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
+       priv->smu_tables.entry[WMTABLE].table_addr_high =
+                       smu_upper_32_bits(mc_addr);
+       priv->smu_tables.entry[WMTABLE].table_addr_low =
+                       smu_lower_32_bits(mc_addr);
+       priv->smu_tables.entry[WMTABLE].table = kaddr;
+       priv->smu_tables.entry[WMTABLE].handle = handle;
+
+       /* allocate space for watermarks table */
+       smu_allocate_memory(smumgr->device,
+                       sizeof(DpmClocks_t),
+                       CGS_GPU_MEM_TYPE__GART_CACHEABLE,
+                       PAGE_SIZE,
+                       &mc_addr,
+                       &kaddr,
+                       &handle);
+
+       PP_ASSERT_WITH_CODE(kaddr,
+                       "[rv_smu_init] Out of memory for CLOCKTABLE.",
+                       cgs_free_gpu_mem(smumgr->device,
+                       (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
+                       kfree(smumgr->backend);
+                       smumgr->backend = NULL;
+                       return -EINVAL);
+
+       priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
+       priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
+       priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
+       priv->smu_tables.entry[CLOCKTABLE].table_addr_high =
+                       smu_upper_32_bits(mc_addr);
+       priv->smu_tables.entry[CLOCKTABLE].table_addr_low =
+                       smu_lower_32_bits(mc_addr);
+       priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
+       priv->smu_tables.entry[CLOCKTABLE].handle = handle;
+
+       return 0;
+}
+
+const struct pp_smumgr_func rv_smu_funcs = {
+       .smu_init = &rv_smu_init,
+       .smu_fini = &rv_smu_fini,
+       .start_smu = &rv_start_smu,
+       .request_smu_load_specific_fw = NULL,
+       .send_msg_to_smc = &rv_send_msg_to_smc,
+       .send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter,
+       .download_pptable_settings = NULL,
+       .upload_pptable_settings = NULL,
+};
+
+
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
new file mode 100644 (file)
index 0000000..262c8de
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef PP_RAVEN_SMUMANAGER_H
+#define PP_RAVEN_SMUMANAGER_H
+
+#include "rv_ppsmc.h"
+#include "smu10_driver_if.h"
+
+enum SMU_TABLE_ID {
+       WMTABLE = 0,
+       CLOCKTABLE,
+       MAX_SMU_TABLE,
+};
+
+struct smu_table_entry {
+       uint32_t version;
+       uint32_t size;
+       uint32_t table_id;
+       uint32_t table_addr_high;
+       uint32_t table_addr_low;
+       uint8_t *table;
+       uint32_t handle;
+};
+
+struct smu_table_array {
+       struct smu_table_entry entry[MAX_SMU_TABLE];
+};
+
+struct rv_smumgr {
+       struct smu_table_array            smu_tables;
+};
+
+int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
+bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
+int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+               uint8_t *table, int16_t table_id);
+int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+               uint8_t *table, int16_t table_id);
+
+
+#endif
index c0d75766bbc8804bcc4c02c1b96387e7cdc7f192..c23402908adf9a5f0027009ed710ae1125cf8b40 100644 (file)
@@ -95,6 +95,15 @@ int smum_early_init(struct pp_instance *handle)
                        return -EINVAL;
                }
                break;
+       case AMDGPU_FAMILY_RV:
+               switch (smumgr->chip_id) {
+               case CHIP_RAVEN:
+                       smumgr->smumgr_funcs = &rv_smu_funcs;
+                       break;
+               default:
+                       return -EINVAL;
+               }
+               break;
        default:
                kfree(smumgr);
                return -EINVAL;