--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMBA_PL08X=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_GEMINI=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MOXART is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+# CONFIG_ARCH_MULTI_V5 is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BOUNCE=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,19200n8"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_GEMINI=y
+CONFIG_COMPACTION=y
+CONFIG_COMPAT_BRK=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_FA=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FA=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_FA526=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_TLB_FA=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+# CONFIG_DMA_NOOP_OPS is not set
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+# CONFIG_DMA_VIRT_OPS is not set
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_LIB_RANDOM is not set
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DST_CACHE=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_EXPERT is not set
+CONFIG_EXPORTFS=y
+CONFIG_EXT4_FS=y
+CONFIG_FARADAY_FTINTC010=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTTMR010_TIMER=y
+CONFIG_FTWDT010_WATCHDOG=y
+CONFIG_FUTEX_PI=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GEMINI_ETHERNET=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INITRAMFS_FORCE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_MCE_KBD_DECODER=y
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_SANYO_DECODER=y
+CONFIG_IR_SHARP_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+CONFIG_IR_XMP_DECODER=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_DLINK_DIR685=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LIBFDT=y
+# CONFIG_LIRC is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+# CONFIG_MEMCG is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF_GEMINI=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_DSA=y
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_NS=y
+CONFIG_NET_PACKET_ENGINE=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_OABI_COMPAT=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_PACKET is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PATA_FTIDE010=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GEMINI=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GEMINI_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_QTNFMAC_PEARL_PCIE is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DECODERS=y
+# CONFIG_RC_DEVICES is not set
+CONFIG_RC_MAP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_FTRTC010=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_GEMINI=y
+CONFIG_SATA_PMP=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SRCU=y
+# CONFIG_STAGING is not set
+# CONFIG_STRICT_KERNEL_RWX is not set
+# CONFIG_STRICT_MODULE_RWX is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKS_RCU=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THIN_ARCHIVES=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUN=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_FOTG210_HCD=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USERIO is not set
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFAT_FS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VLAN_8021Q is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_WLAN_VENDOR_RALINK=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_INFLATE=y
--- /dev/null
+From 57615e112aba6ae4c831d50e769c2c102f013686 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Tue, 7 Jun 2016 22:53:24 +0200
+Subject: [PATCH 01/31] cache patch from OpenWRT
+
+---
+ arch/arm/mm/cache-fa.S | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/mm/cache-fa.S
++++ b/arch/arm/mm/cache-fa.S
+@@ -24,7 +24,8 @@
+ /*
+ * The size of one data cache line.
+ */
+-#define CACHE_DLINESIZE 16
++#define CACHE_DLINESIZE 16
++#define CACHE_DLINESHIFT 4
+
+ /*
+ * The total size of the data cache.
+@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
+ * - start - virtual start address
+ * - end - virtual end address
+ */
++__flush_whole_dcache:
++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
++ mov r0, #0
++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
++ mov pc, lr
++
+ fa_dma_inv_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ tst r0, #CACHE_DLINESIZE - 1
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
+@@ -193,6 +204,10 @@ fa_dma_inv_range:
+ * - end - virtual end address
+ */
+ fa_dma_clean_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
+ add r0, r0, #CACHE_DLINESIZE
--- /dev/null
+From fd7823e6993f440930e9cb85e56375be5823485c Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 14 Oct 2017 17:13:03 +0200
+Subject: [PATCH 02/31] pinctrl: gemini: Add missing functions
+
+Some two functions were missing from the Gemini pin control
+driver. Noticed when trying to use ethernet. Fix it up by
+adding them.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2074,6 +2074,16 @@ static const struct gemini_pmx_func gemi
+ .num_groups = ARRAY_SIZE(satagrps),
+ },
+ {
++ .name = "usb",
++ .groups = usbgrps,
++ .num_groups = ARRAY_SIZE(usbgrps),
++ },
++ {
++ .name = "gmii",
++ .groups = gmiigrps,
++ .num_groups = ARRAY_SIZE(gmiigrps),
++ },
++ {
+ .name = "pci",
+ .groups = pcigrps,
+ .num_groups = ARRAY_SIZE(pcigrps),
--- /dev/null
+From 00e53d08bbe92051765c5bb94223b6f628cd3740 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 11 Oct 2017 19:45:19 +0200
+Subject: [PATCH 03/31] ARM: dts: Add TVE200 to the Gemini SoC DTSI
+
+The Faraday TVE200 is present in the Gemini SoC, sometimes
+under the name "TVC". Add it to the SoC DTSI file along with
+its resources.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ arch/arm/boot/dts/gemini.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -142,6 +142,12 @@
+ groups = "idegrp";
+ };
+ };
++ tvc_default_pins: pinctrl-tvc {
++ mux {
++ function = "tvc";
++ groups = "tvcgrp";
++ };
++ };
+ };
+ };
+
+@@ -348,5 +354,20 @@
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
++
++ display-controller@6a000000 {
++ compatible = "cortina,gemini-tvc", "faraday,tve200";
++ reg = <0x6a000000 0x1000>;
++ interrupts = <13 IRQ_TYPE_EDGE_RISING>;
++ resets = <&syscon GEMINI_RESET_TVC>;
++ clocks = <&syscon GEMINI_CLK_GATE_TVC>,
++ <&syscon GEMINI_CLK_TVC>;
++ clock-names = "PCLK", "TVE";
++ pinctrl-names = "default";
++ pinctrl-0 = <&tvc_default_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
+ };
+ };
--- /dev/null
+From eb3742c4250c6a79e7080bdb6286e5df50c7f26a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:17 +0200
+Subject: [PATCH 04/31] pinctrl: Add skew-delay pin config and bindings
+
+Some pin controllers (such as the Gemini) can control the
+expected clock skew and output delay on certain pins with a
+sub-nanosecond granularity. This is typically done by shunting
+in a number of double inverters in front of or behind the pin.
+Make it possible to configure this with a generic binding.
+
+Cc: devicetree@vger.kernel.org
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 4 ++++
+ drivers/pinctrl/pinconf-generic.c | 2 ++
+ include/linux/pinctrl/pinconf-generic.h | 5 +++++
+ 3 files changed, 11 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
++++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+@@ -271,6 +271,10 @@ output-high - set the pin to output mod
+ sleep-hardware-state - indicate this is sleep related state which will be programmed
+ into the registers for the sleep state.
+ slew-rate - set the slew rate
++skew-delay - this affects the expected clock skew on input pins
++ and the delay before latching a value to an output
++ pin. Typically indicates how many double-inverters are
++ used to delay the signal.
+
+ For example:
+
+--- a/drivers/pinctrl/pinconf-generic.c
++++ b/drivers/pinctrl/pinconf-generic.c
+@@ -49,6 +49,7 @@ static const struct pin_config_item conf
+ PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
+ PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
+ PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
++ PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
+ };
+
+ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
+@@ -181,6 +182,7 @@ static const struct pinconf_generic_para
+ { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
+ { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
++ { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
+ };
+
+ /**
+--- a/include/linux/pinctrl/pinconf-generic.h
++++ b/include/linux/pinctrl/pinconf-generic.h
+@@ -90,6 +90,10 @@
+ * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
+ * this parameter (on a custom format) tells the driver which alternative
+ * slew rate to use.
++ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
++ * or latch delay (on outputs) this parameter (in a custom format)
++ * specifies the clock skew or latch delay. It typically controls how
++ * many double inverters are put in front of the line.
+ * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ * you need to pass in custom configurations to the pin controller, use
+ * PIN_CONFIG_END+1 as the base offset.
+@@ -117,6 +121,7 @@ enum pin_config_param {
+ PIN_CONFIG_POWER_SOURCE,
+ PIN_CONFIG_SLEEP_HARDWARE_STATE,
+ PIN_CONFIG_SLEW_RATE,
++ PIN_CONFIG_SKEW_DELAY,
+ PIN_CONFIG_END = 0x7F,
+ PIN_CONFIG_MAX = 0xFF,
+ };
--- /dev/null
+From 09240ae27ffca65518f7b9d2360c020c1b1ddabe Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:18 +0200
+Subject: [PATCH 05/31] pinctrl: gemini: Use generic DT parser
+
+We can just use the generic Device Tree parser code
+in this driver and save some code.
+
+Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/Kconfig | 1 +
+ drivers/pinctrl/pinctrl-gemini.c | 66 +++-------------------------------------
+ 2 files changed, 5 insertions(+), 62 deletions(-)
+
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -153,6 +153,7 @@ config PINCTRL_GEMINI
+ depends on ARCH_GEMINI
+ default ARCH_GEMINI
+ select PINMUX
++ select GENERIC_PINCONF
+ select MFD_SYSCON
+
+ config PINCTRL_MCP23S08
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -13,6 +13,8 @@
+ #include <linux/pinctrl/machine.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ #include <linux/regmap.h>
+@@ -1918,73 +1920,13 @@ static void gemini_pin_dbg_show(struct p
+ seq_printf(s, " " DRIVER_NAME);
+ }
+
+-static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+- struct device_node *np,
+- struct pinctrl_map **map,
+- unsigned int *reserved_maps,
+- unsigned int *num_maps)
+-{
+- int ret;
+- const char *function = NULL;
+- const char *group;
+- struct property *prop;
+-
+- ret = of_property_read_string(np, "function", &function);
+- if (ret < 0)
+- return ret;
+-
+- ret = of_property_count_strings(np, "groups");
+- if (ret < 0)
+- return ret;
+-
+- ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
+- num_maps, ret);
+- if (ret < 0)
+- return ret;
+-
+- of_property_for_each_string(np, "groups", prop, group) {
+- ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps,
+- num_maps, group, function);
+- if (ret < 0)
+- return ret;
+- pr_debug("ADDED FUNCTION %s <-> GROUP %s\n",
+- function, group);
+- }
+-
+- return 0;
+-}
+-
+-static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+- struct device_node *np_config,
+- struct pinctrl_map **map,
+- unsigned int *num_maps)
+-{
+- unsigned int reserved_maps = 0;
+- struct device_node *np;
+- int ret;
+-
+- *map = NULL;
+- *num_maps = 0;
+-
+- for_each_child_of_node(np_config, np) {
+- ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map,
+- &reserved_maps, num_maps);
+- if (ret < 0) {
+- pinctrl_utils_free_map(pctldev, *map, *num_maps);
+- return ret;
+- }
+- }
+-
+- return 0;
+-};
+-
+ static const struct pinctrl_ops gemini_pctrl_ops = {
+ .get_groups_count = gemini_get_groups_count,
+ .get_group_name = gemini_get_group_name,
+ .get_group_pins = gemini_get_group_pins,
+ .pin_dbg_show = gemini_pin_dbg_show,
+- .dt_node_to_map = gemini_pinctrl_dt_node_to_map,
+- .dt_free_map = pinctrl_utils_free_map,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
++ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
+ /**
--- /dev/null
+From 43e8f011ddbb293e0a3394d0f39819ea2ead4a1b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:19 +0200
+Subject: [PATCH 06/31] pinctrl: gemini: Implement clock skew/delay config
+
+This enabled pin config on the Gemini driver and implements
+pin skew/delay so that the ethernet pins clocking can be
+properly configured.
+
+Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 10 +-
+ drivers/pinctrl/pinctrl-gemini.c | 178 ++++++++++++++++++++-
+ 2 files changed, 182 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+@@ -9,8 +9,14 @@ The pin controller node must be a subnod
+ Required properties:
+ - compatible: "cortina,gemini-pinctrl"
+
+-Subnodes of the pin controller contain pin control multiplexing set-up.
+-Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
++Subnodes of the pin controller contain pin control multiplexing set-up
++and pin configuration of individual pins.
++
++Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
++and generic pin config nodes.
++
++Supported configurations:
++- skew-delay is supported on the Ethernet pins
+
+ Example:
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -24,6 +24,19 @@
+ #define DRIVER_NAME "pinctrl-gemini"
+
+ /**
++ * struct gemini_pin_conf - information about configuring a pin
++ * @pin: the pin number
++ * @reg: config register
++ * @mask: the bits affecting the configuration of the pin
++ */
++struct gemini_pin_conf {
++ unsigned int pin;
++ u32 reg;
++ u32 mask;
++};
++
++/**
++ * struct gemini_pmx - state holder for the gemini pin controller
+ * @dev: a pointer back to containing device
+ * @virtbase: the offset to the controller in virtual memory
+ * @map: regmap to access registers
+@@ -31,6 +44,8 @@
+ * @is_3516: whether the SoC/package is the 3516 variant
+ * @flash_pin: whether the flash pin (extended pins for parallel
+ * flash) is set
++ * @confs: pin config information
++ * @nconfs: number of pin config information items
+ */
+ struct gemini_pmx {
+ struct device *dev;
+@@ -39,6 +54,8 @@ struct gemini_pmx {
+ bool is_3512;
+ bool is_3516;
+ bool flash_pin;
++ const struct gemini_pin_conf *confs;
++ unsigned int nconfs;
+ };
+
+ /**
+@@ -59,6 +76,13 @@ struct gemini_pin_group {
+ u32 value;
+ };
+
++/* Some straight-forward control registers */
++#define GLOBAL_WORD_ID 0x00
++#define GLOBAL_STATUS 0x04
++#define GLOBAL_STATUS_FLPIN BIT(20)
++#define GLOBAL_GMAC_CTRL_SKEW 0x1c
++#define GLOBAL_GMAC0_DATA_SKEW 0x20
++#define GLOBAL_GMAC1_DATA_SKEW 0x24
+ /*
+ * Global Miscellaneous Control Register
+ * This register controls all Gemini pad/pin multiplexing
+@@ -71,9 +95,6 @@ struct gemini_pin_group {
+ * DISABLED again. So you select a flash configuration once, and then
+ * you are stuck with it.
+ */
+-#define GLOBAL_WORD_ID 0x00
+-#define GLOBAL_STATUS 0x04
+-#define GLOBAL_STATUS_FLPIN BIT(20)
+ #define GLOBAL_MISC_CTRL 0x30
+ #define TVC_CLK_PAD_ENABLE BIT(20)
+ #define PCI_CLK_PAD_ENABLE BIT(17)
+@@ -1925,7 +1946,7 @@ static const struct pinctrl_ops gemini_p
+ .get_group_name = gemini_get_group_name,
+ .get_group_pins = gemini_get_group_pins,
+ .pin_dbg_show = gemini_pin_dbg_show,
+- .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
+@@ -2203,10 +2224,155 @@ static const struct pinmux_ops gemini_pm
+ .set_mux = gemini_pmx_set_mux,
+ };
+
++#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
++ .pin = _n, \
++ .reg = _r, \
++ .mask = GENMASK(_hb, _lb) \
++}
++
++static const struct gemini_pin_conf gemini_confs_3512[] = {
++ GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
++ GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
++ GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
++ GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
++ GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
++ GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
++ GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
++ GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
++ GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
++ GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
++ GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
++ GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
++ GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
++ GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
++ GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
++ GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
++ GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
++ GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
++ GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
++ GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
++ GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
++ GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
++ GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
++ GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
++};
++
++static const struct gemini_pin_conf gemini_confs_3516[] = {
++ GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
++ GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
++ GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
++ GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
++ GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
++ GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
++ GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
++ GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
++ GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
++ GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
++ GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
++ GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
++ GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
++ GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
++ GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
++ GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
++ GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
++ GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
++ GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
++ GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
++ GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
++ GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
++ GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
++ GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
++};
++
++static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
++ unsigned int pin)
++{
++ const struct gemini_pin_conf *retconf;
++ int i;
++
++ for (i = 0; i < pmx->nconfs; i++) {
++ retconf = &gemini_confs_3516[i];
++ if (retconf->pin == pin)
++ return retconf;
++ }
++ return NULL;
++}
++
++static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *config)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ enum pin_config_param param = pinconf_to_config_param(*config);
++ const struct gemini_pin_conf *conf;
++ u32 val;
++
++ switch (param) {
++ case PIN_CONFIG_SKEW_DELAY:
++ conf = gemini_get_pin_conf(pmx, pin);
++ if (!conf)
++ return -ENOTSUPP;
++ regmap_read(pmx->map, conf->reg, &val);
++ val &= conf->mask;
++ val >>= (ffs(conf->mask) - 1);
++ *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++
++ return 0;
++}
++
++static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *configs, unsigned int num_configs)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ const struct gemini_pin_conf *conf;
++ enum pin_config_param param;
++ u32 arg;
++ int ret = 0;
++ int i;
++
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ arg = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_SKEW_DELAY:
++ if (arg > 0xf)
++ return -EINVAL;
++ conf = gemini_get_pin_conf(pmx, pin);
++ if (!conf) {
++ dev_err(pmx->dev,
++ "invalid pin for skew delay %d\n", pin);
++ return -ENOTSUPP;
++ }
++ arg <<= (ffs(conf->mask) - 1);
++ dev_dbg(pmx->dev,
++ "set pin %d to skew delay mask %08x, val %08x\n",
++ pin, conf->mask, arg);
++ regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
++ break;
++ default:
++ dev_err(pmx->dev, "Invalid config param %04x\n", param);
++ return -ENOTSUPP;
++ }
++ }
++
++ return ret;
++}
++
++static const struct pinconf_ops gemini_pinconf_ops = {
++ .pin_config_get = gemini_pinconf_get,
++ .pin_config_set = gemini_pinconf_set,
++ .is_generic = true,
++};
++
+ static struct pinctrl_desc gemini_pmx_desc = {
+ .name = DRIVER_NAME,
+ .pctlops = &gemini_pctrl_ops,
+ .pmxops = &gemini_pmx_ops,
++ .confops = &gemini_pinconf_ops,
+ .owner = THIS_MODULE,
+ };
+
+@@ -2249,11 +2415,15 @@ static int gemini_pmx_probe(struct platf
+ val &= 0xffff;
+ if (val == 0x3512) {
+ pmx->is_3512 = true;
++ pmx->confs = gemini_confs_3512;
++ pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
+ gemini_pmx_desc.pins = gemini_3512_pins;
+ gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
+ dev_info(dev, "detected 3512 chip variant\n");
+ } else if (val == 0x3516) {
+ pmx->is_3516 = true;
++ pmx->confs = gemini_confs_3516;
++ pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
+ gemini_pmx_desc.pins = gemini_3516_pins;
+ gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
+ dev_info(dev, "detected 3516 chip variant\n");
--- /dev/null
+From e7759c44e0c20dd6b5a259300acdc7350ea6dd32 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 6 Nov 2017 21:27:34 +0100
+Subject: [PATCH 07/31] pinctrl: gemini: Fix GMAC groups
+
+The GMII groups need to be split across GMAC0 and GMAC1 since
+GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7
+so we might want just one interface out.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++-------------
+ 1 file changed, 54 insertions(+), 25 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -96,6 +96,13 @@ struct gemini_pin_group {
+ * you are stuck with it.
+ */
+ #define GLOBAL_MISC_CTRL 0x30
++#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
++/* Not really used */
++#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
++/* Activated with GMAC1 */
++#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
++/* This will be the default */
++#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
+ #define TVC_CLK_PAD_ENABLE BIT(20)
+ #define PCI_CLK_PAD_ENABLE BIT(17)
+ #define LPC_CLK_PAD_ENABLE BIT(16)
+@@ -109,8 +116,8 @@ struct gemini_pin_group {
+ #define NAND_PADS_DISABLE BIT(2)
+ #define PFLASH_PADS_DISABLE BIT(1)
+ #define SFLASH_PADS_DISABLE BIT(0)
+-#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
+-#define PADS_MAXBIT 20
++#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
++#define PADS_MAXBIT 27
+
+ /* Ordered by bit index */
+ static const char * const gemini_padgroups[] = {
+@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[
+ };
+
+ /* GMII, ethernet pins */
+-static const unsigned int gmii_3512_pins[] = {
+- 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
+- 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
++static const unsigned int gmii_gmac0_3512_pins[] = {
++ 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
++};
++
++static const unsigned int gmii_gmac1_3512_pins[] = {
++ 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
+ };
+
+ static const unsigned int pci_3512_pins[] = {
+@@ -668,10 +678,10 @@ static const unsigned int gpio1c_3512_pi
+ /* The GPIO1D (28-31) pins overlap with LCD and TVC */
+ static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
+
+-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
++/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
+ static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
+
+-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
++/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
+ static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
+
+ /* The GPIO2C (8-31) pins overlap with PCI */
+@@ -738,9 +748,16 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(usb_3512_pins),
+ },
+ {
+- .name = "gmiigrp",
+- .pins = gmii_3512_pins,
+- .num_pins = ARRAY_SIZE(gmii_3512_pins),
++ .name = "gmii_gmac0_grp",
++ .pins = gmii_gmac0_3512_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
++ },
++ {
++ .name = "gmii_gmac1_grp",
++ .pins = gmii_gmac1_3512_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
++ /* Bring out RGMII on the GMAC1 pins */
++ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "pcigrp",
+@@ -954,14 +971,15 @@ static const struct gemini_pin_group gem
+ .name = "gpio2agrp",
+ .pins = gpio2a_3512_pins,
+ .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
+- /* Conflict with GMII and extended parallel flash */
++ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ /* Conflict with GMII GMAC1 and extended parallel flash */
+ },
+ {
+ .name = "gpio2bgrp",
+ .pins = gpio2b_3512_pins,
+ .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
+- /* Conflict with GMII, extended parallel flash and LCD */
+- .mask = LCD_PADS_ENABLE,
++ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
++ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "gpio2cgrp",
+@@ -1441,9 +1459,12 @@ static const unsigned int usb_3516_pins[
+ };
+
+ /* GMII, ethernet pins */
+-static const unsigned int gmii_3516_pins[] = {
+- 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
+- 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
++static const unsigned int gmii_gmac0_3516_pins[] = {
++ 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
++};
++
++static const unsigned int gmii_gmac1_3516_pins[] = {
++ 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
+ };
+
+ static const unsigned int pci_3516_pins[] = {
+@@ -1585,10 +1606,10 @@ static const unsigned int gpio1c_3516_pi
+ /* The GPIO1D (28-31) pins overlap with TVC */
+ static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
+
+-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
++/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
+ static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
+
+-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
++/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
+ static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
+
+ /* The GPIO2C (8-31) pins overlap with PCI */
+@@ -1660,9 +1681,16 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(usb_3516_pins),
+ },
+ {
+- .name = "gmiigrp",
+- .pins = gmii_3516_pins,
+- .num_pins = ARRAY_SIZE(gmii_3516_pins),
++ .name = "gmii_gmac0_grp",
++ .pins = gmii_gmac0_3516_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
++ },
++ {
++ .name = "gmii_gmac1_grp",
++ .pins = gmii_gmac1_3516_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
++ /* Bring out RGMII on the GMAC1 pins */
++ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "pcigrp",
+@@ -1861,14 +1889,15 @@ static const struct gemini_pin_group gem
+ .name = "gpio2agrp",
+ .pins = gpio2a_3516_pins,
+ .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
+- /* Conflict with GMII and extended parallel flash */
++ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ /* Conflict with GMII GMAC1 and extended parallel flash */
+ },
+ {
+ .name = "gpio2bgrp",
+ .pins = gpio2b_3516_pins,
+ .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
+- /* Conflict with GMII, extended parallel flash and LCD */
+- .mask = LCD_PADS_ENABLE,
++ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
++ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "gpio2cgrp",
+@@ -1971,7 +2000,7 @@ static const char * const icegrps[] = {
+ static const char * const idegrps[] = { "idegrp" };
+ static const char * const satagrps[] = { "satagrp" };
+ static const char * const usbgrps[] = { "usbgrp" };
+-static const char * const gmiigrps[] = { "gmiigrp" };
++static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
+ static const char * const pcigrps[] = { "pcigrp" };
+ static const char * const lpcgrps[] = { "lpcgrp" };
+ static const char * const lcdgrps[] = { "lcdgrp" };
--- /dev/null
+From 3f2941cb12a6d6a0ef4e53e0ecb8d2431d352964 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 13 Nov 2017 22:36:12 +0100
+Subject: [PATCH 08/31] pinctrl: gemini: Fix missing pad descriptions
+
+A pretty clever static checker found a bug in my patch: I added more
+bits to a bitmask but didn't extend the array indexed to the same
+bitmask.
+
+Fixes: 756a024f3983 ("pinctrl: gemini: Fix GMAC groups")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -136,6 +136,8 @@ static const char * const gemini_padgrou
+ "PCI CLK",
+ NULL, NULL,
+ "TVC CLK",
++ NULL, NULL, NULL, NULL, NULL,
++ "GMAC1",
+ };
+
+ static const struct pinctrl_pin_desc gemini_3512_pins[] = {
--- /dev/null
+From c25653d045ce86c5ae472258fdaa39a6baaf75eb Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 19 Nov 2017 10:57:27 +0100
+Subject: [PATCH 09/31] pinctrl: gemini: Add two missing GPIO groups
+
+The 3512 has two more GPIO groups on GPIO area 0, so let's
+make it possible to combine these with the function.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2015,7 +2015,8 @@ static const char * const sflashgrps[] =
+ static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
+ "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
+ "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
+- "gpio0jgrp", "gpio0kgrp" };
++ "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
++ "gpio0mgrp" };
+ static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
+ "gpio1dgrp" };
+ static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
--- /dev/null
+From 88a5c6ad311588f178c5a88e4eeacc6d40b8ede3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 22 Nov 2017 21:04:14 +0100
+Subject: [PATCH 10/31] pinctrl: gemini: Fix usage of 3512 groups
+
+The pin config lookup function was still hardcoding the
+3516 pin set, which is obviously wrong. Use the pointer
+in the state container.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2323,7 +2323,7 @@ static const struct gemini_pin_conf *gem
+ int i;
+
+ for (i = 0; i < pmx->nconfs; i++) {
+- retconf = &gemini_confs_3516[i];
++ retconf = &pmx->confs[i];
+ if (retconf->pin == pin)
+ return retconf;
+ }
--- /dev/null
+From f147cf49ef39f5e87d5df9ef1fab52683bc75c63 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 2 Dec 2017 12:23:09 +0100
+Subject: [PATCH 11/31] pinctrl: gemini: Support drive strength setting
+
+The Gemini pin controller can set drive strength for a few
+select groups of pins (not individually). Implement this
+for GMAC0 and 1 (ethernet ports), IDE and PCI.
+
+Cc: devicetree@vger.kernel.org
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 3 +
+ drivers/pinctrl/pinctrl-gemini.c | 81 ++++++++++++++++++++++
+ 2 files changed, 84 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+@@ -17,6 +17,9 @@ and generic pin config nodes.
+
+ Supported configurations:
+ - skew-delay is supported on the Ethernet pins
++- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
++ entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
++ and "pcigrp".
+
+ Example:
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -67,6 +67,9 @@ struct gemini_pmx {
+ * elements in .pins so we can iterate over that array
+ * @mask: bits to clear to enable this when doing pin muxing
+ * @value: bits to set to enable this when doing pin muxing
++ * @driving_mask: bitmask for the IO Pad driving register for this
++ * group, if it supports altering the driving strength of
++ * its lines.
+ */
+ struct gemini_pin_group {
+ const char *name;
+@@ -74,12 +77,14 @@ struct gemini_pin_group {
+ const unsigned int num_pins;
+ u32 mask;
+ u32 value;
++ u32 driving_mask;
+ };
+
+ /* Some straight-forward control registers */
+ #define GLOBAL_WORD_ID 0x00
+ #define GLOBAL_STATUS 0x04
+ #define GLOBAL_STATUS_FLPIN BIT(20)
++#define GLOBAL_IODRIVE 0x10
+ #define GLOBAL_GMAC_CTRL_SKEW 0x1c
+ #define GLOBAL_GMAC0_DATA_SKEW 0x20
+ #define GLOBAL_GMAC1_DATA_SKEW 0x24
+@@ -738,6 +743,7 @@ static const struct gemini_pin_group gem
+ /* Conflict with all flash usage */
+ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
+ PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
++ .driving_mask = GENMASK(21, 20),
+ },
+ {
+ .name = "satagrp",
+@@ -753,6 +759,7 @@ static const struct gemini_pin_group gem
+ .name = "gmii_gmac0_grp",
+ .pins = gmii_gmac0_3512_pins,
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
++ .driving_mask = GENMASK(17, 16),
+ },
+ {
+ .name = "gmii_gmac1_grp",
+@@ -760,6 +767,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
+ /* Bring out RGMII on the GMAC1 pins */
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ .driving_mask = GENMASK(19, 18),
+ },
+ {
+ .name = "pcigrp",
+@@ -767,6 +775,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(pci_3512_pins),
+ /* Conflict only with GPIO2 */
+ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
++ .driving_mask = GENMASK(23, 22),
+ },
+ {
+ .name = "lpcgrp",
+@@ -1671,6 +1680,7 @@ static const struct gemini_pin_group gem
+ /* Conflict with all flash usage */
+ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
+ PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
++ .driving_mask = GENMASK(21, 20),
+ },
+ {
+ .name = "satagrp",
+@@ -1686,6 +1696,7 @@ static const struct gemini_pin_group gem
+ .name = "gmii_gmac0_grp",
+ .pins = gmii_gmac0_3516_pins,
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
++ .driving_mask = GENMASK(17, 16),
+ },
+ {
+ .name = "gmii_gmac1_grp",
+@@ -1693,6 +1704,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
+ /* Bring out RGMII on the GMAC1 pins */
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ .driving_mask = GENMASK(19, 18),
+ },
+ {
+ .name = "pcigrp",
+@@ -1700,6 +1712,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(pci_3516_pins),
+ /* Conflict only with GPIO2 */
+ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
++ .driving_mask = GENMASK(23, 22),
+ },
+ {
+ .name = "lpcgrp",
+@@ -2394,9 +2407,77 @@ static int gemini_pinconf_set(struct pin
+ return ret;
+ }
+
++static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
++ unsigned selector,
++ unsigned long *configs,
++ unsigned num_configs)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ const struct gemini_pin_group *grp = NULL;
++ enum pin_config_param param;
++ u32 arg;
++ u32 val;
++ int i;
++
++ if (pmx->is_3512)
++ grp = &gemini_3512_pin_groups[selector];
++ if (pmx->is_3516)
++ grp = &gemini_3516_pin_groups[selector];
++
++ /* First figure out if this group supports configs */
++ if (!grp->driving_mask) {
++ dev_err(pmx->dev, "pin config group \"%s\" does "
++ "not support drive strength setting\n",
++ grp->name);
++ return -EINVAL;
++ }
++
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ arg = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_DRIVE_STRENGTH:
++ switch (arg) {
++ case 4:
++ val = 0;
++ break;
++ case 8:
++ val = 1;
++ break;
++ case 12:
++ val = 2;
++ break;
++ case 16:
++ val = 3;
++ break;
++ default:
++ dev_err(pmx->dev,
++ "invalid drive strength %d mA\n",
++ arg);
++ return -ENOTSUPP;
++ }
++ val <<= (ffs(grp->driving_mask) - 1);
++ regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
++ grp->driving_mask,
++ val);
++ dev_info(pmx->dev,
++ "set group %s to %d mA drive strength mask %08x val %08x\n",
++ grp->name, arg, grp->driving_mask, val);
++ break;
++ default:
++ dev_err(pmx->dev, "invalid config param %04x\n", param);
++ return -ENOTSUPP;
++ }
++ }
++
++ return 0;
++}
++
+ static const struct pinconf_ops gemini_pinconf_ops = {
+ .pin_config_get = gemini_pinconf_get,
+ .pin_config_set = gemini_pinconf_set,
++ .pin_config_group_set = gemini_pinconf_group_set,
+ .is_generic = true,
+ };
+
--- /dev/null
+From f0674df220f3da81c173025636a904b395cf8f8b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 19 Nov 2017 10:46:16 +0100
+Subject: [PATCH 12/31] ARM: dts: Add ethernet PHYs to the a bunch of Geminis
+
+These Gemini boards have Ethernet PHY on GPIO bit-banged
+MDIO, clearly defined in the corresponding OpenWRT
+ethernet patches since ages. Add them in accordance with
+the OpenWRT patch so we can use them when we add ethernet
+support.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini-nas4220b.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-rut1xx.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-wbd111.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 18 ++++++++++++++++++
+ 4 files changed, 57 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -64,6 +64,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ flash@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-rut1xx.dts
++++ b/arch/arm/boot/dts/gemini-rut1xx.dts
+@@ -58,6 +58,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ flash@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -69,6 +69,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ flash@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -69,6 +69,24 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++
++ phy1: ethernet-phy@3 {
++ reg = <3>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ flash@30000000 {
+ status = "okay";
--- /dev/null
+From 2f08de94f207a4347053e1faa22c9a310c9c61b0 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 17 Nov 2017 16:36:32 +0100
+Subject: [PATCH 13/31] ARM: dts: Add basic devicetree for D-Link DNS-313
+
+This adds a basic device tree for the D-Link DNS-313
+NAS enclosure. This device has a thermal sensor and a
+fan so we add a thermal zone for the chassis in the
+device tree based on information from the product.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/gemini-dlink-dns-313.dts | 241 +++++++++++++++++++++++++++++
+ 2 files changed, 242 insertions(+)
+ create mode 100644 arch/arm/boot/dts/gemini-dlink-dns-313.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
+ exynos5800-peach-pi.dtb
+ dtb-$(CONFIG_ARCH_GEMINI) += \
+ gemini-dlink-dir-685.dtb \
++ gemini-dlink-dns-313.dtb \
+ gemini-nas4220b.dtb \
+ gemini-rut1xx.dtb \
+ gemini-sq201.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+@@ -0,0 +1,241 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
++ */
++
++/dts-v1/;
++
++#include "gemini.dtsi"
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++ model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
++ compatible = "dlink,dir-313", "cortina,gemini";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory {
++ /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ aliases {
++ mdio-gpio0 = &mdio0;
++ };
++
++ chosen {
++ stdout-path = "uart0:19200n8";
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ button-esc {
++ debounce_interval = <50>;
++ wakeup-source;
++ linux,code = <KEY_ESC>;
++ label = "reset";
++ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ led-power {
++ label = "dns313:blue:power";
++ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ led-disk-blue {
++ label = "dns313:blue:disk";
++ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ };
++ led-disk-green {
++ label = "dns313:green:disk";
++ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ linux,default-trigger = "ide-disk";
++ /* Ideally should activate while reading */
++ };
++ led-disk-red {
++ label = "dns313:red:disk";
++ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ /* Ideally should activate while writing */
++ };
++ };
++
++ /*
++ * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM.
++ */
++ fan0: gpio-fan {
++ compatible = "gpio-fan";
++ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
++ <&gpio0 12 GPIO_ACTIVE_HIGH>;
++ gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>;
++ cooling-min-level = <0>;
++ cooling-max-level = <2>;
++ #cooling-cells = <2>;
++ };
++
++
++ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
++ gpio-i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ g751: temperature-sensor@48 {
++ compatible = "gmt,g751";
++ reg = <0x48>;
++ #thermal-sensor-cells = <0>;
++ };
++ };
++
++ thermal-zones {
++ chassis-thermal {
++ /* Poll every 20 seconds */
++ polling-delay = <20000>;
++ /* Poll every 2nd second when cooling */
++ polling-delay-passive = <2000>;
++
++ thermal-sensors = <&g751>;
++
++ /* Tripping points from the fan.script in the rootfs */
++ trips {
++ chassis_alert0: chassis-alert0 {
++ /* At 43 degrees turn on low speed */
++ temperature = <43000>;
++ hysteresis = <3000>;
++ type = "active";
++ };
++ chassis_alert1: chassis-alert1 {
++ /* At 47 degrees turn on high speed */
++ temperature = <47000>;
++ hysteresis = <3000>;
++ type = "active";
++ };
++ chassis_crit: chassis-crit {
++ /* Just shut down at 60 degrees */
++ temperature = <60000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&chassis_alert0>;
++ cooling-device = <&fan0 1 1>;
++ };
++ map1 {
++ trip = <&chassis_alert1>;
++ cooling-device = <&fan0 2 2>;
++ };
++ };
++ };
++ };
++
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ /* Uses MDC and MDIO */
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* This is a Realtek RTL8211B Gigabit ethernet transceiver */
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
++ soc {
++ flash@30000000 {
++ status = "okay";
++ /* 512KB of flash */
++ reg = <0x30000000 0x00080000>;
++
++ /*
++ * This "RedBoot" is the Storlink derivative.
++ */
++ partition@0 {
++ label = "RedBoot";
++ reg = <0x00000000 0x00040000>;
++ read-only;
++ };
++ partition@40000 {
++ label = "MTD1";
++ reg = <0x00040000 0x00020000>;
++ read-only;
++ };
++ partition@60000 {
++ label = "MTD2";
++ reg = <0x00060000 0x00020000>;
++ read-only;
++ };
++ };
++
++ syscon: syscon@40000000 {
++ pinctrl {
++ /*
++ */
++ gpio0_default_pins: pinctrl-gpio0 {
++ mux {
++ function = "gpio0";
++ groups =
++ /* Used by LEDs conflicts ICE */
++ "gpio0bgrp",
++ /* Used by ? conflicts ICE */
++ "gpio0cgrp",
++ /*
++ * Used by fan & G751, conflicts LPC,
++ * UART modem lines, SSP
++ */
++ "gpio0egrp",
++ /* Used by G751 */
++ "gpio0fgrp",
++ /* Used by MDIO */
++ "gpio0igrp";
++ };
++ };
++ gpio1_default_pins: pinctrl-gpio1 {
++ mux {
++ function = "gpio1";
++ /* Used by "reset" button */
++ groups = "gpio1dgrp";
++ };
++ };
++ };
++ };
++
++ sata: sata@46000000 {
++ /* The ROM uses this muxmode */
++ cortina,gemini-ata-muxmode = <3>;
++ cortina,gemini-enable-sata-bridge;
++ status = "okay";
++ };
++
++ gpio0: gpio@4d000000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio0_default_pins>;
++ };
++
++ gpio1: gpio@4e000000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio1_default_pins>;
++ };
++
++ ata@63000000 {
++ status = "okay";
++ };
++ };
++};
--- /dev/null
+From eed839dc713fdb7b2579dbfea41d676386b8259b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 10 Sep 2017 20:02:33 +0200
+Subject: [PATCH 14/31] ARM: dts: Flags D-Link DIR-685 I2C bus gpios
+
+These GPIOs are used in open drain mode, so make sure to
+flag them as such. Use the new separate scl/sda line
+GPIO bindings.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -99,8 +99,8 @@
+ gpio-i2c {
+ compatible = "i2c-gpio";
+ /* Collides with ICE */
+- gpios = <&gpio0 5 0>, /* SDA */
+- <&gpio0 6 0>; /* SCL */
++ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
--- /dev/null
+From dec551d2301f71a692ed1729a323c8259d36f849 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 11 Oct 2017 19:49:13 +0200
+Subject: [PATCH 15/31] ARM: dts: Add PCI to WBD111 and WBD222
+
+These two boards have mini-PCI card slots, so enable PCI
+on both of them.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini-wbd111.dts | 22 ++++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 22 ++++++++++++++++++++++
+ 2 files changed, 44 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -138,5 +138,27 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
++
++ pci@50000000 {
++ status = "okay";
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
++ <0x4800 0 0 2 &pci_intc 1>,
++ <0x4800 0 0 3 &pci_intc 2>,
++ <0x4800 0 0 4 &pci_intc 3>,
++ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
++ <0x5000 0 0 2 &pci_intc 2>,
++ <0x5000 0 0 3 &pci_intc 3>,
++ <0x5000 0 0 4 &pci_intc 0>,
++ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
++ <0x5800 0 0 2 &pci_intc 3>,
++ <0x5800 0 0 3 &pci_intc 0>,
++ <0x5800 0 0 4 &pci_intc 1>,
++ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
++ <0x6000 0 0 2 &pci_intc 0>,
++ <0x6000 0 0 3 &pci_intc 1>,
++ <0x6000 0 0 4 &pci_intc 2>;
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -143,5 +143,27 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
++
++ pci@50000000 {
++ status = "okay";
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
++ <0x4800 0 0 2 &pci_intc 1>,
++ <0x4800 0 0 3 &pci_intc 2>,
++ <0x4800 0 0 4 &pci_intc 3>,
++ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
++ <0x5000 0 0 2 &pci_intc 2>,
++ <0x5000 0 0 3 &pci_intc 3>,
++ <0x5000 0 0 4 &pci_intc 0>,
++ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
++ <0x5800 0 0 2 &pci_intc 3>,
++ <0x5800 0 0 3 &pci_intc 0>,
++ <0x5800 0 0 4 &pci_intc 1>,
++ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
++ <0x6000 0 0 2 &pci_intc 0>,
++ <0x6000 0 0 3 &pci_intc 1>,
++ <0x6000 0 0 4 &pci_intc 2>;
++ };
+ };
+ };
--- /dev/null
+From 9d3b968d13ba1eecaf22d5824cf8fd270c061534 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 15 Jul 2017 21:02:06 +0200
+Subject: [PATCH 16/31] ARM: dts: Add TVE/TVC and ILI9322 panel to DIR-685
+
+This adds the TVE200/TVC TV-encoder and the Ilitek ILI9322 panel
+to the DIR-685 device tree.
+
+This brings graphics to this funky router and it is possible to
+even run a console on its tiny screen.
+
+Incidentally this requires us to disable the access to the
+parallel (NOR) flash, as the communication pins to the panel
+are shared with the flash memory.
+
+To access the flash, a separate kernel with the panel disabled
+and the flash enabled should be booted. The pin control selecting
+whether to use the lines cannot be altered at runtime due to
+hardware constraints.
+
+Cc: David Lechner <david@lechnology.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Ben Dooks <ben.dooks@codethink.co.uk>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 63 +++++++++++++++++++++++++++++-
+ 1 file changed, 62 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -45,6 +45,47 @@
+ };
+ };
+
++ vdisp: regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "display-power";
++ regulator-min-microvolt = <3600000>;
++ regulator-max-microvolt = <3600000>;
++ /* Collides with LCD E */
++ gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ spi {
++ compatible = "spi-gpio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* Collides with IDE pins, that's cool (we do not use them) */
++ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
++ /* Collides with pflash CE1, not so cool */
++ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <1>;
++
++ panel: display@0 {
++ compatible = "dlink,dir-685-panel", "ilitek,ili9322";
++ reg = <0>;
++ /* 50 ns min period = 20 MHz */
++ spi-max-frequency = <20000000>;
++ spi-cpol; /* Clock active low */
++ vcc-supply = <&vdisp>;
++ iovcc-supply = <&vdisp>;
++ vci-supply = <&vdisp>;
++
++ port {
++ panel_in: endpoint {
++ remote-endpoint = <&display_out>;
++ };
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ led-wps {
+@@ -115,7 +156,16 @@
+
+ soc {
+ flash@30000000 {
+- status = "okay";
++ /*
++ * Flash access is by default disabled, because it
++ * collides with the Chip Enable signal for the display
++ * panel, that reuse the parallel flash Chip Select 1
++ * (CS1). Enabling flash makes graphics stop working.
++ *
++ * We might be able to hack around this by letting
++ * GPIO poke around in the flash controller registers.
++ */
++ /* status = "okay"; */
+ /* 32MB of flash */
+ reg = <0x30000000 0x02000000>;
+
+@@ -242,5 +292,16 @@
+ ata@63000000 {
+ status = "okay";
+ };
++
++ display-controller@6a000000 {
++ status = "okay";
++
++ port@0 {
++ reg = <0>;
++ display_out: endpoint {
++ remote-endpoint = <&panel_in>;
++ };
++ };
++ };
+ };
+ };
--- /dev/null
+From d73f6cc09bcbe258a72c06899215d1a3e8a7686d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:23 +0200
+Subject: [PATCH 17/31] watchdog: gemini/ftwdt010: rename DT bindings
+
+The device tree bindings are in two copies and also should be
+consolidated into a single Faraday Technology FTWDT010
+binding since we uncovered that this IP part is a standard
+IP from Faraday.
+
+Cc: devicetree@vger.kernel.org
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ .../bindings/watchdog/cortina,gemini-watchdog.txt | 17 -----------------
+ ...{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} | 11 ++++++++---
+ 2 files changed, 8 insertions(+), 20 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
+ rename Documentation/devicetree/bindings/watchdog/{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} (55%)
+
+--- a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
++++ /dev/null
+@@ -1,17 +0,0 @@
+-Cortina Systems Gemini SoC Watchdog
+-
+-Required properties:
+-- compatible : must be "cortina,gemini-watchdog"
+-- reg : shall contain base register location and length
+-- interrupts : shall contain the interrupt for the watchdog
+-
+-Optional properties:
+-- timeout-sec : the default watchdog timeout in seconds.
+-
+-Example:
+-
+-watchdog@41000000 {
+- compatible = "cortina,gemini-watchdog";
+- reg = <0x41000000 0x1000>;
+- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+-};
+--- a/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt
++++ /dev/null
+@@ -1,17 +0,0 @@
+-Cortina Systems Gemini SoC Watchdog
+-
+-Required properties:
+-- compatible : must be "cortina,gemini-watchdog"
+-- reg : shall contain base register location and length
+-- interrupts : shall contain the interrupt for the watchdog
+-
+-Optional properties:
+-- timeout-sec : the default watchdog timeout in seconds.
+-
+-Example:
+-
+-watchdog@41000000 {
+- compatible = "cortina,gemini-watchdog";
+- reg = <0x41000000 0x1000>;
+- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt
+@@ -0,0 +1,22 @@
++Faraday Technology FTWDT010 watchdog
++
++This is an IP part from Faraday Technology found in the Gemini
++SoCs and others.
++
++Required properties:
++- compatible : must be one of
++ "faraday,ftwdt010"
++ "cortina,gemini-watchdog", "faraday,ftwdt010"
++- reg : shall contain base register location and length
++- interrupts : shall contain the interrupt for the watchdog
++
++Optional properties:
++- timeout-sec : the default watchdog timeout in seconds.
++
++Example:
++
++watchdog@41000000 {
++ compatible = "faraday,ftwdt010";
++ reg = <0x41000000 0x1000>;
++ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
++};
--- /dev/null
+From c197a5a04d658da490de08636066a6bdbebf16c5 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:24 +0200
+Subject: [PATCH 18/31] watchdog: gemini/ftwdt010: rename driver and symbols
+
+This renames all the driver files and symbols for the Gemini
+watchdog to FTWDT010 as it has been revealed that this IP block
+is a generic watchdog timer from Faraday Technology used in
+several SoC designs.
+
+Select this driver by default for the Gemini, it is a sensible
+driver to always have enabled.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ drivers/watchdog/Kconfig | 14 +--
+ drivers/watchdog/Makefile | 2 +-
+ drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} | 117 +++++++++++-----------
+ 3 files changed, 68 insertions(+), 65 deletions(-)
+ rename drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} (50%)
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -321,16 +321,18 @@ config 977_WATCHDOG
+
+ Not sure? It's safe to say N.
+
+-config GEMINI_WATCHDOG
+- tristate "Gemini watchdog"
+- depends on ARCH_GEMINI
++config FTWDT010_WATCHDOG
++ tristate "Faraday Technology FTWDT010 watchdog"
++ depends on ARM || COMPILE_TEST
+ select WATCHDOG_CORE
++ default ARCH_GEMINI
+ help
+- Say Y here if to include support for the watchdog timer
+- embedded in the Cortina Systems Gemini family of devices.
++ Say Y here if to include support for the Faraday Technology
++ FTWDT010 watchdog timer embedded in the Cortina Systems Gemini
++ family of devices.
+
+ To compile this driver as a module, choose M here: the
+- module will be called gemini_wdt.
++ module will be called ftwdt010_wdt.
+
+ config IXP4XX_WATCHDOG
+ tristate "IXP4xx Watchdog"
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -46,7 +46,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
+ obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
+ obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
+ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
+-obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
++obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+ obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
+ obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
+ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+--- a/drivers/watchdog/gemini_wdt.c
++++ /dev/null
+@@ -1,229 +0,0 @@
+-/*
+- * Watchdog driver for Cortina Systems Gemini SoC
+- *
+- * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
+- *
+- * Inspired by the out-of-tree drivers from OpenWRT:
+- * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/bitops.h>
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+-#include <linux/io.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/of_device.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-#include <linux/watchdog.h>
+-
+-#define GEMINI_WDCOUNTER 0x0
+-#define GEMINI_WDLOAD 0x4
+-#define GEMINI_WDRESTART 0x8
+-#define GEMINI_WDCR 0xC
+-
+-#define WDRESTART_MAGIC 0x5AB9
+-
+-#define WDCR_CLOCK_5MHZ BIT(4)
+-#define WDCR_SYS_RST BIT(1)
+-#define WDCR_ENABLE BIT(0)
+-
+-#define WDT_CLOCK 5000000 /* 5 MHz */
+-
+-struct gemini_wdt {
+- struct watchdog_device wdd;
+- struct device *dev;
+- void __iomem *base;
+-};
+-
+-static inline
+-struct gemini_wdt *to_gemini_wdt(struct watchdog_device *wdd)
+-{
+- return container_of(wdd, struct gemini_wdt, wdd);
+-}
+-
+-static int gemini_wdt_start(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(wdd->timeout * WDT_CLOCK, gwdt->base + GEMINI_WDLOAD);
+- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART);
+- /* set clock before enabling */
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
+- gwdt->base + GEMINI_WDCR);
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
+- gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_stop(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(0, gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_ping(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_set_timeout(struct watchdog_device *wdd,
+- unsigned int timeout)
+-{
+- wdd->timeout = timeout;
+- if (watchdog_active(wdd))
+- gemini_wdt_start(wdd);
+-
+- return 0;
+-}
+-
+-static irqreturn_t gemini_wdt_interrupt(int irq, void *data)
+-{
+- struct gemini_wdt *gwdt = data;
+-
+- watchdog_notify_pretimeout(&gwdt->wdd);
+-
+- return IRQ_HANDLED;
+-}
+-
+-static const struct watchdog_ops gemini_wdt_ops = {
+- .start = gemini_wdt_start,
+- .stop = gemini_wdt_stop,
+- .ping = gemini_wdt_ping,
+- .set_timeout = gemini_wdt_set_timeout,
+- .owner = THIS_MODULE,
+-};
+-
+-static const struct watchdog_info gemini_wdt_info = {
+- .options = WDIOF_KEEPALIVEPING
+- | WDIOF_MAGICCLOSE
+- | WDIOF_SETTIMEOUT,
+- .identity = KBUILD_MODNAME,
+-};
+-
+-
+-static int gemini_wdt_probe(struct platform_device *pdev)
+-{
+- struct device *dev = &pdev->dev;
+- struct resource *res;
+- struct gemini_wdt *gwdt;
+- unsigned int reg;
+- int irq;
+- int ret;
+-
+- gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
+- if (!gwdt)
+- return -ENOMEM;
+-
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- gwdt->base = devm_ioremap_resource(dev, res);
+- if (IS_ERR(gwdt->base))
+- return PTR_ERR(gwdt->base);
+-
+- irq = platform_get_irq(pdev, 0);
+- if (!irq)
+- return -EINVAL;
+-
+- gwdt->dev = dev;
+- gwdt->wdd.info = &gemini_wdt_info;
+- gwdt->wdd.ops = &gemini_wdt_ops;
+- gwdt->wdd.min_timeout = 1;
+- gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
+- gwdt->wdd.parent = dev;
+-
+- /*
+- * If 'timeout-sec' unspecified in devicetree, assume a 13 second
+- * default.
+- */
+- gwdt->wdd.timeout = 13U;
+- watchdog_init_timeout(&gwdt->wdd, 0, dev);
+-
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- if (reg & WDCR_ENABLE) {
+- /* Watchdog was enabled by the bootloader, disable it. */
+- reg &= ~WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+- }
+-
+- ret = devm_request_irq(dev, irq, gemini_wdt_interrupt, 0,
+- "watchdog bark", gwdt);
+- if (ret)
+- return ret;
+-
+- ret = devm_watchdog_register_device(dev, &gwdt->wdd);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to register watchdog\n");
+- return ret;
+- }
+-
+- /* Set up platform driver data */
+- platform_set_drvdata(pdev, gwdt);
+- dev_info(dev, "Gemini watchdog driver enabled\n");
+-
+- return 0;
+-}
+-
+-static int __maybe_unused gemini_wdt_suspend(struct device *dev)
+-{
+- struct gemini_wdt *gwdt = dev_get_drvdata(dev);
+- unsigned int reg;
+-
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- reg &= ~WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int __maybe_unused gemini_wdt_resume(struct device *dev)
+-{
+- struct gemini_wdt *gwdt = dev_get_drvdata(dev);
+- unsigned int reg;
+-
+- if (watchdog_active(&gwdt->wdd)) {
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- reg |= WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+- }
+-
+- return 0;
+-}
+-
+-static const struct dev_pm_ops gemini_wdt_dev_pm_ops = {
+- SET_SYSTEM_SLEEP_PM_OPS(gemini_wdt_suspend,
+- gemini_wdt_resume)
+-};
+-
+-#ifdef CONFIG_OF
+-static const struct of_device_id gemini_wdt_match[] = {
+- { .compatible = "cortina,gemini-watchdog" },
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, gemini_wdt_match);
+-#endif
+-
+-static struct platform_driver gemini_wdt_driver = {
+- .probe = gemini_wdt_probe,
+- .driver = {
+- .name = "gemini-wdt",
+- .of_match_table = of_match_ptr(gemini_wdt_match),
+- .pm = &gemini_wdt_dev_pm_ops,
+- },
+-};
+-module_platform_driver(gemini_wdt_driver);
+-MODULE_AUTHOR("Linus Walleij");
+-MODULE_DESCRIPTION("Watchdog driver for Gemini");
+-MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/watchdog/ftwdt010_wdt.c
+@@ -0,0 +1,230 @@
++/*
++ * Watchdog driver for Faraday Technology FTWDT010
++ *
++ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
++ *
++ * Inspired by the out-of-tree drivers from OpenWRT:
++ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/bitops.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/watchdog.h>
++
++#define FTWDT010_WDCOUNTER 0x0
++#define FTWDT010_WDLOAD 0x4
++#define FTWDT010_WDRESTART 0x8
++#define FTWDT010_WDCR 0xC
++
++#define WDRESTART_MAGIC 0x5AB9
++
++#define WDCR_CLOCK_5MHZ BIT(4)
++#define WDCR_SYS_RST BIT(1)
++#define WDCR_ENABLE BIT(0)
++
++#define WDT_CLOCK 5000000 /* 5 MHz */
++
++struct ftwdt010_wdt {
++ struct watchdog_device wdd;
++ struct device *dev;
++ void __iomem *base;
++};
++
++static inline
++struct ftwdt010_wdt *to_ftwdt010_wdt(struct watchdog_device *wdd)
++{
++ return container_of(wdd, struct ftwdt010_wdt, wdd);
++}
++
++static int ftwdt010_wdt_start(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
++ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
++ /* set clock before enabling */
++ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
++ gwdt->base + FTWDT010_WDCR);
++ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
++ gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_stop(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(0, gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_ping(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_set_timeout(struct watchdog_device *wdd,
++ unsigned int timeout)
++{
++ wdd->timeout = timeout;
++ if (watchdog_active(wdd))
++ ftwdt010_wdt_start(wdd);
++
++ return 0;
++}
++
++static irqreturn_t ftwdt010_wdt_interrupt(int irq, void *data)
++{
++ struct ftwdt010_wdt *gwdt = data;
++
++ watchdog_notify_pretimeout(&gwdt->wdd);
++
++ return IRQ_HANDLED;
++}
++
++static const struct watchdog_ops ftwdt010_wdt_ops = {
++ .start = ftwdt010_wdt_start,
++ .stop = ftwdt010_wdt_stop,
++ .ping = ftwdt010_wdt_ping,
++ .set_timeout = ftwdt010_wdt_set_timeout,
++ .owner = THIS_MODULE,
++};
++
++static const struct watchdog_info ftwdt010_wdt_info = {
++ .options = WDIOF_KEEPALIVEPING
++ | WDIOF_MAGICCLOSE
++ | WDIOF_SETTIMEOUT,
++ .identity = KBUILD_MODNAME,
++};
++
++
++static int ftwdt010_wdt_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ struct ftwdt010_wdt *gwdt;
++ unsigned int reg;
++ int irq;
++ int ret;
++
++ gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
++ if (!gwdt)
++ return -ENOMEM;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ gwdt->base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(gwdt->base))
++ return PTR_ERR(gwdt->base);
++
++ irq = platform_get_irq(pdev, 0);
++ if (!irq)
++ return -EINVAL;
++
++ gwdt->dev = dev;
++ gwdt->wdd.info = &ftwdt010_wdt_info;
++ gwdt->wdd.ops = &ftwdt010_wdt_ops;
++ gwdt->wdd.min_timeout = 1;
++ gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
++ gwdt->wdd.parent = dev;
++
++ /*
++ * If 'timeout-sec' unspecified in devicetree, assume a 13 second
++ * default.
++ */
++ gwdt->wdd.timeout = 13U;
++ watchdog_init_timeout(&gwdt->wdd, 0, dev);
++
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ if (reg & WDCR_ENABLE) {
++ /* Watchdog was enabled by the bootloader, disable it. */
++ reg &= ~WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++ }
++
++ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
++ "watchdog bark", gwdt);
++ if (ret)
++ return ret;
++
++ ret = devm_watchdog_register_device(dev, &gwdt->wdd);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register watchdog\n");
++ return ret;
++ }
++
++ /* Set up platform driver data */
++ platform_set_drvdata(pdev, gwdt);
++ dev_info(dev, "FTWDT010 watchdog driver enabled\n");
++
++ return 0;
++}
++
++static int __maybe_unused ftwdt010_wdt_suspend(struct device *dev)
++{
++ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
++ unsigned int reg;
++
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ reg &= ~WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int __maybe_unused ftwdt010_wdt_resume(struct device *dev)
++{
++ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
++ unsigned int reg;
++
++ if (watchdog_active(&gwdt->wdd)) {
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ reg |= WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++ }
++
++ return 0;
++}
++
++static const struct dev_pm_ops ftwdt010_wdt_dev_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ftwdt010_wdt_suspend,
++ ftwdt010_wdt_resume)
++};
++
++#ifdef CONFIG_OF
++static const struct of_device_id ftwdt010_wdt_match[] = {
++ { .compatible = "faraday,ftwdt010" },
++ { .compatible = "cortina,gemini-watchdog" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ftwdt010_wdt_match);
++#endif
++
++static struct platform_driver ftwdt010_wdt_driver = {
++ .probe = ftwdt010_wdt_probe,
++ .driver = {
++ .name = "ftwdt010-wdt",
++ .of_match_table = of_match_ptr(ftwdt010_wdt_match),
++ .pm = &ftwdt010_wdt_dev_pm_ops,
++ },
++};
++module_platform_driver(ftwdt010_wdt_driver);
++MODULE_AUTHOR("Linus Walleij");
++MODULE_DESCRIPTION("Watchdog driver for Faraday Technology FTWDT010");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 4347a0b0699989b889857c9d4ccfbce339859f13 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:25 +0200
+Subject: [PATCH 19/31] watchdog: ftwdt010: Make interrupt optional
+
+The Moxart does not appear to be using the interrupt from the
+watchdog timer, maybe it's not even routed, so as to support
+more architectures with this driver, make the interrupt
+optional.
+
+While we are at it: actually enable the use of the interrupt
+if present by setting the right bit in the control register
+and define the missing control register bits.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ drivers/watchdog/ftwdt010_wdt.c | 30 ++++++++++++++++++------------
+ 1 file changed, 18 insertions(+), 12 deletions(-)
+
+--- a/drivers/watchdog/ftwdt010_wdt.c
++++ b/drivers/watchdog/ftwdt010_wdt.c
+@@ -30,6 +30,8 @@
+ #define WDRESTART_MAGIC 0x5AB9
+
+ #define WDCR_CLOCK_5MHZ BIT(4)
++#define WDCR_WDEXT BIT(3)
++#define WDCR_WDINTR BIT(2)
+ #define WDCR_SYS_RST BIT(1)
+ #define WDCR_ENABLE BIT(0)
+
+@@ -39,6 +41,7 @@ struct ftwdt010_wdt {
+ struct watchdog_device wdd;
+ struct device *dev;
+ void __iomem *base;
++ bool has_irq;
+ };
+
+ static inline
+@@ -50,14 +53,17 @@ struct ftwdt010_wdt *to_ftwdt010_wdt(str
+ static int ftwdt010_wdt_start(struct watchdog_device *wdd)
+ {
+ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++ u32 enable;
+
+ writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
+ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
+ /* set clock before enabling */
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
+- gwdt->base + FTWDT010_WDCR);
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
+- gwdt->base + FTWDT010_WDCR);
++ enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST;
++ writel(enable, gwdt->base + FTWDT010_WDCR);
++ if (gwdt->has_irq)
++ enable |= WDCR_WDINTR;
++ enable |= WDCR_ENABLE;
++ writel(enable, gwdt->base + FTWDT010_WDCR);
+
+ return 0;
+ }
+@@ -133,10 +139,6 @@ static int ftwdt010_wdt_probe(struct pla
+ if (IS_ERR(gwdt->base))
+ return PTR_ERR(gwdt->base);
+
+- irq = platform_get_irq(pdev, 0);
+- if (!irq)
+- return -EINVAL;
+-
+ gwdt->dev = dev;
+ gwdt->wdd.info = &ftwdt010_wdt_info;
+ gwdt->wdd.ops = &ftwdt010_wdt_ops;
+@@ -158,10 +160,14 @@ static int ftwdt010_wdt_probe(struct pla
+ writel(reg, gwdt->base + FTWDT010_WDCR);
+ }
+
+- ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
+- "watchdog bark", gwdt);
+- if (ret)
+- return ret;
++ irq = platform_get_irq(pdev, 0);
++ if (irq) {
++ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
++ "watchdog bark", gwdt);
++ if (ret)
++ return ret;
++ gwdt->has_irq = true;
++ }
+
+ ret = devm_watchdog_register_device(dev, &gwdt->wdd);
+ if (ret) {
--- /dev/null
+From b0a88a861b036124ef2d6acfe6dd87cfde63e750 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 22 Dec 2017 00:19:08 +0100
+Subject: [PATCH 20/31] soc: Add SoC driver for Gemini
+
+This adds an SoC driver for the Gemini. Currently there
+is only one thing not fitting into any other framework,
+and that is the bus arbitration setting.
+
+All Gemini vendor trees seem to be setting this register to
+exactly the same arbitration so we just add a small code
+snippet to do this at subsys_init() time before any other
+drivers kick in.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ drivers/soc/Makefile | 1 +
+ drivers/soc/gemini/Makefile | 2 ++
+ drivers/soc/gemini/soc-gemini.c | 71 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+)
+ create mode 100644 drivers/soc/gemini/Makefile
+ create mode 100644 drivers/soc/gemini/soc-gemini.c
+
+--- a/drivers/soc/Makefile
++++ b/drivers/soc/Makefile
+@@ -9,6 +9,7 @@ obj-y += bcm/
+ obj-$(CONFIG_ARCH_DOVE) += dove/
+ obj-$(CONFIG_MACH_DOVE) += dove/
+ obj-y += fsl/
++obj-$(CONFIG_ARCH_GEMINI) += gemini/
+ obj-$(CONFIG_ARCH_MXC) += imx/
+ obj-$(CONFIG_SOC_XWAY) += lantiq/
+ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+--- /dev/null
++++ b/drivers/soc/gemini/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-y += soc-gemini.o
+--- /dev/null
++++ b/drivers/soc/gemini/soc-gemini.c
+@@ -0,0 +1,71 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2017 Linaro Ltd.
++ *
++ * Author: Linus Walleij <linus.walleij@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2, as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
++#include <linux/of.h>
++
++#define GLOBAL_WORD_ID 0x00
++#define GEMINI_GLOBAL_ARB1_CTRL 0x2c
++#define GEMINI_ARB1_BURST_MASK GENMASK(21, 16)
++#define GEMINI_ARB1_BURST_SHIFT 16
++/* These all define the priority on the BUS2 backplane */
++#define GEMINI_ARB1_PRIO_MASK GENMASK(9, 0)
++#define GEMINI_ARB1_DMAC_HIGH_PRIO BIT(0)
++#define GEMINI_ARB1_IDE_HIGH_PRIO BIT(1)
++#define GEMINI_ARB1_RAID_HIGH_PRIO BIT(2)
++#define GEMINI_ARB1_SECURITY_HIGH_PRIO BIT(3)
++#define GEMINI_ARB1_GMAC0_HIGH_PRIO BIT(4)
++#define GEMINI_ARB1_GMAC1_HIGH_PRIO BIT(5)
++#define GEMINI_ARB1_USB0_HIGH_PRIO BIT(6)
++#define GEMINI_ARB1_USB1_HIGH_PRIO BIT(7)
++#define GEMINI_ARB1_PCI_HIGH_PRIO BIT(8)
++#define GEMINI_ARB1_TVE_HIGH_PRIO BIT(9)
++
++#define GEMINI_DEFAULT_BURST_SIZE 0x20
++#define GEMINI_DEFAULT_PRIO (GEMINI_ARB1_GMAC0_HIGH_PRIO | \
++ GEMINI_ARB1_GMAC1_HIGH_PRIO)
++
++static int __init gemini_soc_init(void)
++{
++ struct regmap *map;
++ u32 rev;
++ u32 val;
++ int ret;
++
++ /* Multiplatform guard, only proceed on Gemini */
++ if (!of_machine_is_compatible("cortina,gemini"))
++ return 0;
++
++ map = syscon_regmap_lookup_by_compatible("cortina,gemini-syscon");
++ if (IS_ERR(map))
++ return PTR_ERR(map);
++ ret = regmap_read(map, GLOBAL_WORD_ID, &rev);
++ if (ret)
++ return ret;
++
++ val = (GEMINI_DEFAULT_BURST_SIZE << GEMINI_ARB1_BURST_SHIFT) |
++ GEMINI_DEFAULT_PRIO;
++
++ /* Set up system arbitration */
++ regmap_update_bits(map,
++ GEMINI_GLOBAL_ARB1_CTRL,
++ GEMINI_ARB1_BURST_MASK | GEMINI_ARB1_PRIO_MASK,
++ val);
++
++ pr_info("Gemini SoC %04x revision %02x, set arbitration %08x\n",
++ rev >> 8, rev & 0xff, val);
++
++ return 0;
++}
++subsys_initcall(gemini_soc_init);
--- /dev/null
+From 49bc597009f52ec8970269f6201d3ed415a844ee Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 12 Jan 2018 22:34:23 +0100
+Subject: [PATCH 21/31] net: ethernet: Add DT bindings for the Gemini ethernet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds the device tree bindings for the Gemini ethernet
+controller. It is pretty straight-forward, using standard
+bindings and modelling the two child ports as child devices
+under the parent ethernet controller device.
+
+Cc: devicetree@vger.kernel.org
+Cc: Tobias Waldvogel <tobias.waldvogel@gmail.com>
+Cc: Michał Mirosław <mirq-linux@rere.qmqm.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../bindings/net/cortina,gemini-ethernet.txt | 92 ++++++++++++++++++++++
+ 1 file changed, 92 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+@@ -0,0 +1,92 @@
++Cortina Systems Gemini Ethernet Controller
++==========================================
++
++This ethernet controller is found in the Gemini SoC family:
++StorLink SL3512 and SL3516, also known as Cortina Systems
++CS3512 and CS3516.
++
++Required properties:
++- compatible: must be "cortina,gemini-ethernet"
++- reg: must contain the global registers and the V-bit and A-bit
++ memory areas, in total three register sets.
++- syscon: a phandle to the system controller
++- #address-cells: must be specified, must be <1>
++- #size-cells: must be specified, must be <1>
++- ranges: should be state like this giving a 1:1 address translation
++ for the subnodes
++
++The subnodes represents the two ethernet ports in this device.
++They are not independent of each other since they share resources
++in the parent node, and are thus children.
++
++Required subnodes:
++- port0: contains the resources for ethernet port 0
++- port1: contains the resources for ethernet port 1
++
++Required subnode properties:
++- compatible: must be "cortina,gemini-ethernet-port"
++- reg: must contain two register areas: the DMA/TOE memory and
++ the GMAC memory area of the port
++- interrupts: should contain the interrupt line of the port.
++ this is nominally a level interrupt active high.
++- resets: this must provide an SoC-integrated reset line for
++ the port.
++- clocks: this should contain a handle to the PCLK clock for
++ clocking the silicon in this port
++- clock-names: must be "PCLK"
++
++Optional subnode properties:
++- phy-mode: see ethernet.txt
++- phy-handle: see ethernet.txt
++
++Example:
++
++mdio-bus {
++ (...)
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ phy1: ethernet-phy@3 {
++ reg = <3>;
++ device_type = "ethernet-phy";
++ };
++};
++
++
++ethernet@60000000 {
++ compatible = "cortina,gemini-ethernet";
++ reg = <0x60000000 0x4000>, /* Global registers, queue */
++ <0x60004000 0x2000>, /* V-bit */
++ <0x60006000 0x2000>; /* A-bit */
++ syscon = <&syscon>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ gmac0: ethernet-port@0 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
++ <0x6000a000 0x2000>; /* Port 0 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC0>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
++ clock-names = "PCLK";
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++
++ gmac1: ethernet-port@1 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
++ <0x6000e000 0x2000>; /* Port 1 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC1>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
++ clock-names = "PCLK";
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++};
--- /dev/null
+From 07826b86d4ce4d35fd1674d7f78e4b2060ab2910 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 12 Jan 2018 22:34:24 +0100
+Subject: [PATCH 22/31] net: ethernet: Add a driver for Gemini gigabit ethernet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Gemini ethernet has been around for years as an out-of-tree
+patch used with the NAS boxen and routers built on StorLink
+SL3512 and SL3516, later Storm Semiconductor, later Cortina
+Systems. These ASICs are still being deployed and brand new
+off-the-shelf systems using it can easily be acquired.
+
+The full name of the IP block is "Net Engine and Gigabit
+Ethernet MAC" commonly just called "GMAC".
+
+The hardware block contains a common TCP Offload Enginer (TOE)
+that can be used by both MACs. The current driver does not use
+it.
+
+Cc: Tobias Waldvogel <tobias.waldvogel@gmail.com>
+Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 2 +
+ drivers/net/ethernet/Kconfig | 1 +
+ drivers/net/ethernet/Makefile | 1 +
+ drivers/net/ethernet/cortina/Kconfig | 22 +
+ drivers/net/ethernet/cortina/Makefile | 4 +
+ drivers/net/ethernet/cortina/gemini.c | 2593 +++++++++++++++++++++++++++++++++
+ drivers/net/ethernet/cortina/gemini.h | 958 ++++++++++++
+ 7 files changed, 3581 insertions(+)
+ create mode 100644 drivers/net/ethernet/cortina/Kconfig
+ create mode 100644 drivers/net/ethernet/cortina/Makefile
+ create mode 100644 drivers/net/ethernet/cortina/gemini.c
+ create mode 100644 drivers/net/ethernet/cortina/gemini.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1327,8 +1327,10 @@ T: git git://github.com/ulli-kroll/linux
+ S: Maintained
+ F: Documentation/devicetree/bindings/arm/gemini.txt
+ F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+ F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
+ F: arch/arm/mach-gemini/
++F: drivers/net/ethernet/cortina/gemini/*
+ F: drivers/pinctrl/pinctrl-gemini.c
+ F: drivers/rtc/rtc-ftrtc010.c
+
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -42,6 +42,7 @@ source "drivers/net/ethernet/cavium/Kcon
+ source "drivers/net/ethernet/chelsio/Kconfig"
+ source "drivers/net/ethernet/cirrus/Kconfig"
+ source "drivers/net/ethernet/cisco/Kconfig"
++source "drivers/net/ethernet/cortina/Kconfig"
+
+ config CX_ECAT
+ tristate "Beckhoff CX5020 EtherCAT master support"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_VENDOR_CAVIUM) += caviu
+ obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
+ obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
+ obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
++obj-$(CONFIG_NET_VENDOR_CORTINA) += cortina/
+ obj-$(CONFIG_CX_ECAT) += ec_bhf.o
+ obj-$(CONFIG_DM9000) += davicom/
+ obj-$(CONFIG_DNET) += dnet.o
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/Kconfig
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0
++# Cortina ethernet devices
++
++config NET_VENDOR_CORTINA
++ bool "Cortina Gemini devices"
++ default y
++ ---help---
++ If you have a network (Ethernet) card belonging to this class, say Y
++ and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++if NET_VENDOR_CORTINA
++
++config GEMINI_ETHERNET
++ tristate "Gemini Gigabit Ethernet support"
++ depends on OF
++ select PHYLIB
++ select CRC32
++ ---help---
++ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
++
++endif # NET_VENDOR_CORTINA
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for the Cortina Gemini network device drivers.
++
++obj-$(CONFIG_GEMINI_ETHERNET) += gemini.o
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -0,0 +1,2593 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Ethernet device driver for Cortina Systems Gemini SoC
++ * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
++ * Net Engine and Gigabit Ethernet MAC (GMAC)
++ * This hardware contains a TCP Offload Engine (TOE) but currently the
++ * driver does not make use of it.
++ *
++ * Authors:
++ * Linus Walleij <linus.walleij@linaro.org>
++ * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
++ * Michał Mirosław <mirq-linux@rere.qmqm.pl>
++ * Paulius Zaleckas <paulius.zaleckas@gmail.com>
++ * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
++ * Gary Chen & Ch Hsu Storlink Semiconductor
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++#include <linux/cache.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/of_mdio.h>
++#include <linux/of_net.h>
++#include <linux/of_platform.h>
++#include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
++#include <linux/skbuff.h>
++#include <linux/phy.h>
++#include <linux/crc32.h>
++#include <linux/ethtool.h>
++#include <linux/tcp.h>
++#include <linux/u64_stats_sync.h>
++
++#include <linux/in.h>
++#include <linux/ip.h>
++#include <linux/ipv6.h>
++
++#include "gemini.h"
++
++#define DRV_NAME "gmac-gemini"
++#define DRV_VERSION "1.0"
++
++#define HSIZE_8 0x00
++#define HSIZE_16 0x01
++#define HSIZE_32 0x02
++
++#define HBURST_SINGLE 0x00
++#define HBURST_INCR 0x01
++#define HBURST_INCR4 0x02
++#define HBURST_INCR8 0x03
++
++#define HPROT_DATA_CACHE BIT(0)
++#define HPROT_PRIVILIGED BIT(1)
++#define HPROT_BUFFERABLE BIT(2)
++#define HPROT_CACHABLE BIT(3)
++
++#define DEFAULT_RX_COALESCE_NSECS 0
++#define DEFAULT_GMAC_RXQ_ORDER 9
++#define DEFAULT_GMAC_TXQ_ORDER 8
++#define DEFAULT_RX_BUF_ORDER 11
++#define DEFAULT_NAPI_WEIGHT 64
++#define TX_MAX_FRAGS 16
++#define TX_QUEUE_NUM 1 /* max: 6 */
++#define RX_MAX_ALLOC_ORDER 2
++
++#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
++ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
++#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
++ GMAC0_SWTQ00_FIN_INT_BIT)
++#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
++
++#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
++
++/**
++ * struct gmac_queue_page - page buffer per-page info
++ */
++struct gmac_queue_page {
++ struct page *page;
++ dma_addr_t mapping;
++};
++
++struct gmac_txq {
++ struct gmac_txdesc *ring;
++ struct sk_buff **skb;
++ unsigned int cptr;
++ unsigned int noirq_packets;
++};
++
++struct gemini_ethernet;
++
++struct gemini_ethernet_port {
++ u8 id; /* 0 or 1 */
++
++ struct gemini_ethernet *geth;
++ struct net_device *netdev;
++ struct device *dev;
++ void __iomem *dma_base;
++ void __iomem *gmac_base;
++ struct clk *pclk;
++ struct reset_control *reset;
++ int irq;
++ __le32 mac_addr[3];
++
++ void __iomem *rxq_rwptr;
++ struct gmac_rxdesc *rxq_ring;
++ unsigned int rxq_order;
++
++ struct napi_struct napi;
++ struct hrtimer rx_coalesce_timer;
++ unsigned int rx_coalesce_nsecs;
++ unsigned int freeq_refill;
++ struct gmac_txq txq[TX_QUEUE_NUM];
++ unsigned int txq_order;
++ unsigned int irq_every_tx_packets;
++
++ dma_addr_t rxq_dma_base;
++ dma_addr_t txq_dma_base;
++
++ unsigned int msg_enable;
++ spinlock_t config_lock; /* Locks config register */
++
++ struct u64_stats_sync tx_stats_syncp;
++ struct u64_stats_sync rx_stats_syncp;
++ struct u64_stats_sync ir_stats_syncp;
++
++ struct rtnl_link_stats64 stats;
++ u64 hw_stats[RX_STATS_NUM];
++ u64 rx_stats[RX_STATUS_NUM];
++ u64 rx_csum_stats[RX_CHKSUM_NUM];
++ u64 rx_napi_exits;
++ u64 tx_frag_stats[TX_MAX_FRAGS];
++ u64 tx_frags_linearized;
++ u64 tx_hw_csummed;
++};
++
++struct gemini_ethernet {
++ struct device *dev;
++ void __iomem *base;
++ struct gemini_ethernet_port *port0;
++ struct gemini_ethernet_port *port1;
++
++ spinlock_t irq_lock; /* Locks IRQ-related registers */
++ unsigned int freeq_order;
++ unsigned int freeq_frag_order;
++ struct gmac_rxdesc *freeq_ring;
++ dma_addr_t freeq_dma_base;
++ struct gmac_queue_page *freeq_pages;
++ unsigned int num_freeq_pages;
++ spinlock_t freeq_lock; /* Locks queue from reentrance */
++};
++
++#define GMAC_STATS_NUM ( \
++ RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
++ TX_MAX_FRAGS + 2)
++
++static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
++ "GMAC_IN_DISCARDS",
++ "GMAC_IN_ERRORS",
++ "GMAC_IN_MCAST",
++ "GMAC_IN_BCAST",
++ "GMAC_IN_MAC1",
++ "GMAC_IN_MAC2",
++ "RX_STATUS_GOOD_FRAME",
++ "RX_STATUS_TOO_LONG_GOOD_CRC",
++ "RX_STATUS_RUNT_FRAME",
++ "RX_STATUS_SFD_NOT_FOUND",
++ "RX_STATUS_CRC_ERROR",
++ "RX_STATUS_TOO_LONG_BAD_CRC",
++ "RX_STATUS_ALIGNMENT_ERROR",
++ "RX_STATUS_TOO_LONG_BAD_ALIGN",
++ "RX_STATUS_RX_ERR",
++ "RX_STATUS_DA_FILTERED",
++ "RX_STATUS_BUFFER_FULL",
++ "RX_STATUS_11",
++ "RX_STATUS_12",
++ "RX_STATUS_13",
++ "RX_STATUS_14",
++ "RX_STATUS_15",
++ "RX_CHKSUM_IP_UDP_TCP_OK",
++ "RX_CHKSUM_IP_OK_ONLY",
++ "RX_CHKSUM_NONE",
++ "RX_CHKSUM_3",
++ "RX_CHKSUM_IP_ERR_UNKNOWN",
++ "RX_CHKSUM_IP_ERR",
++ "RX_CHKSUM_TCP_UDP_ERR",
++ "RX_CHKSUM_7",
++ "RX_NAPI_EXITS",
++ "TX_FRAGS[1]",
++ "TX_FRAGS[2]",
++ "TX_FRAGS[3]",
++ "TX_FRAGS[4]",
++ "TX_FRAGS[5]",
++ "TX_FRAGS[6]",
++ "TX_FRAGS[7]",
++ "TX_FRAGS[8]",
++ "TX_FRAGS[9]",
++ "TX_FRAGS[10]",
++ "TX_FRAGS[11]",
++ "TX_FRAGS[12]",
++ "TX_FRAGS[13]",
++ "TX_FRAGS[14]",
++ "TX_FRAGS[15]",
++ "TX_FRAGS[16+]",
++ "TX_FRAGS_LINEARIZED",
++ "TX_HW_CSUMMED",
++};
++
++static void gmac_dump_dma_state(struct net_device *netdev);
++
++static void gmac_update_config0_reg(struct net_device *netdev,
++ u32 val, u32 vmask)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg = (reg & ~vmask) | val;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_enable_tx_rx(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg &= ~CONFIG0_TX_RX_DISABLE;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_disable_tx_rx(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ val = readl(port->gmac_base + GMAC_CONFIG0);
++ val |= CONFIG0_TX_RX_DISABLE;
++ writel(val, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++
++ mdelay(10); /* let GMAC consume packet */
++}
++
++static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ val = readl(port->gmac_base + GMAC_CONFIG0);
++ val &= ~CONFIG0_FLOW_CTL;
++ if (tx)
++ val |= CONFIG0_FLOW_TX;
++ if (rx)
++ val |= CONFIG0_FLOW_RX;
++ writel(val, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_speed_set(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct phy_device *phydev = netdev->phydev;
++ union gmac_status status, old_status;
++ int pause_tx = 0;
++ int pause_rx = 0;
++
++ status.bits32 = readl(port->gmac_base + GMAC_STATUS);
++ old_status.bits32 = status.bits32;
++ status.bits.link = phydev->link;
++ status.bits.duplex = phydev->duplex;
++
++ switch (phydev->speed) {
++ case 1000:
++ status.bits.speed = GMAC_SPEED_1000;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
++ netdev_info(netdev, "connect to RGMII @ 1Gbit\n");
++ break;
++ case 100:
++ status.bits.speed = GMAC_SPEED_100;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII @ 100 Mbit\n");
++ break;
++ case 10:
++ status.bits.speed = GMAC_SPEED_10;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII @ 10 Mbit\n");
++ break;
++ default:
++ netdev_warn(netdev, "Not supported PHY speed (%d)\n",
++ phydev->speed);
++ }
++
++ if (phydev->duplex == DUPLEX_FULL) {
++ u16 lcladv = phy_read(phydev, MII_ADVERTISE);
++ u16 rmtadv = phy_read(phydev, MII_LPA);
++ u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
++
++ if (cap & FLOW_CTRL_RX)
++ pause_rx = 1;
++ if (cap & FLOW_CTRL_TX)
++ pause_tx = 1;
++ }
++
++ gmac_set_flow_control(netdev, pause_tx, pause_rx);
++
++ if (old_status.bits32 == status.bits32)
++ return;
++
++ if (netif_msg_link(port)) {
++ phy_print_status(phydev);
++ netdev_info(netdev, "link flow control: %s\n",
++ phydev->pause
++ ? (phydev->asym_pause ? "tx" : "both")
++ : (phydev->asym_pause ? "rx" : "none")
++ );
++ }
++
++ gmac_disable_tx_rx(netdev);
++ writel(status.bits32, port->gmac_base + GMAC_STATUS);
++ gmac_enable_tx_rx(netdev);
++}
++
++static int gmac_setup_phy(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_status status = { .bits32 = 0 };
++ struct device *dev = port->dev;
++ struct phy_device *phy;
++
++ phy = of_phy_get_and_connect(netdev,
++ dev->of_node,
++ gmac_speed_set);
++ if (!phy)
++ return -ENODEV;
++ netdev->phydev = phy;
++
++ netdev_info(netdev, "connected to PHY \"%s\"\n",
++ phydev_name(phy));
++ phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
++ (unsigned long)phy->phy_id,
++ phy_modes(phy->interface));
++
++ phy->supported &= PHY_GBIT_FEATURES;
++ phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
++ phy->advertising = phy->supported;
++
++ /* set PHY interface type */
++ switch (phy->interface) {
++ case PHY_INTERFACE_MODE_MII:
++ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
++ status.bits.mii_rmii = GMAC_PHY_MII;
++ netdev_info(netdev, "connect to MII\n");
++ break;
++ case PHY_INTERFACE_MODE_GMII:
++ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
++ status.bits.mii_rmii = GMAC_PHY_GMII;
++ netdev_info(netdev, "connect to GMII\n");
++ break;
++ case PHY_INTERFACE_MODE_RGMII:
++ dev_info(dev, "set GMAC0 and GMAC1 to MII/RGMII mode\n");
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII\n");
++ break;
++ default:
++ netdev_err(netdev, "Unsupported MII interface\n");
++ phy_disconnect(phy);
++ netdev->phydev = NULL;
++ return -EINVAL;
++ }
++ writel(status.bits32, port->gmac_base + GMAC_STATUS);
++
++ return 0;
++}
++
++static int gmac_pick_rx_max_len(int max_l3_len)
++{
++ /* index = CONFIG_MAXLEN_XXX values */
++ static const int max_len[8] = {
++ 1536, 1518, 1522, 1542,
++ 9212, 10236, 1518, 1518
++ };
++ int i, n = 5;
++
++ max_l3_len += ETH_HLEN + VLAN_HLEN;
++
++ if (max_l3_len > max_len[n])
++ return -1;
++
++ for (i = 0; i < 5; i++) {
++ if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
++ n = i;
++ }
++
++ return n;
++}
++
++static int gmac_init(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0 = { .bits = {
++ .dis_tx = 1,
++ .dis_rx = 1,
++ .ipv4_rx_chksum = 1,
++ .ipv6_rx_chksum = 1,
++ .rx_err_detect = 1,
++ .rgmm_edge = 1,
++ .port0_chk_hwq = 1,
++ .port1_chk_hwq = 1,
++ .port0_chk_toeq = 1,
++ .port1_chk_toeq = 1,
++ .port0_chk_classq = 1,
++ .port1_chk_classq = 1,
++ } };
++ union gmac_ahb_weight ahb_weight = { .bits = {
++ .rx_weight = 1,
++ .tx_weight = 1,
++ .hash_weight = 1,
++ .pre_req = 0x1f,
++ .tq_dv_threshold = 0,
++ } };
++ union gmac_tx_wcr0 hw_weigh = { .bits = {
++ .hw_tq3 = 1,
++ .hw_tq2 = 1,
++ .hw_tq1 = 1,
++ .hw_tq0 = 1,
++ } };
++ union gmac_tx_wcr1 sw_weigh = { .bits = {
++ .sw_tq5 = 1,
++ .sw_tq4 = 1,
++ .sw_tq3 = 1,
++ .sw_tq2 = 1,
++ .sw_tq1 = 1,
++ .sw_tq0 = 1,
++ } };
++ union gmac_config1 config1 = { .bits = {
++ .set_threshold = 16,
++ .rel_threshold = 24,
++ } };
++ union gmac_config2 config2 = { .bits = {
++ .set_threshold = 16,
++ .rel_threshold = 32,
++ } };
++ union gmac_config3 config3 = { .bits = {
++ .set_threshold = 0,
++ .rel_threshold = 0,
++ } };
++ union gmac_config0 tmp;
++ u32 val;
++
++ config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
++ tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++ config0.bits.reserved = tmp.bits.reserved;
++ writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
++ writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
++ writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
++ writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
++
++ val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
++ writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
++
++ writel(hw_weigh.bits32,
++ port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
++ writel(sw_weigh.bits32,
++ port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
++
++ port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
++ port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
++ port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
++
++ /* Mark every quarter of the queue a packet for interrupt
++ * in order to be able to wake up the queue if it was stopped
++ */
++ port->irq_every_tx_packets = 1 << (port->txq_order - 2);
++
++ return 0;
++}
++
++static void gmac_uninit(struct net_device *netdev)
++{
++ if (netdev->phydev)
++ phy_disconnect(netdev->phydev);
++}
++
++static int gmac_setup_txqs(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int n_txq = netdev->num_tx_queues;
++ struct gemini_ethernet *geth = port->geth;
++ size_t entries = 1 << port->txq_order;
++ struct gmac_txq *txq = port->txq;
++ struct gmac_txdesc *desc_ring;
++ size_t len = n_txq * entries;
++ struct sk_buff **skb_tab;
++ void __iomem *rwptr_reg;
++ unsigned int r;
++ int i;
++
++ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
++ if (!skb_tab)
++ return -ENOMEM;
++
++ desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
++ &port->txq_dma_base, GFP_KERNEL);
++
++ if (!desc_ring) {
++ kfree(skb_tab);
++ return -ENOMEM;
++ }
++
++ if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
++ dev_warn(geth->dev, "TX queue base it not aligned\n");
++ return -ENOMEM;
++ }
++
++ writel(port->txq_dma_base | port->txq_order,
++ port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
++
++ for (i = 0; i < n_txq; i++) {
++ txq->ring = desc_ring;
++ txq->skb = skb_tab;
++ txq->noirq_packets = 0;
++
++ r = readw(rwptr_reg);
++ rwptr_reg += 2;
++ writew(r, rwptr_reg);
++ rwptr_reg += 2;
++ txq->cptr = r;
++
++ txq++;
++ desc_ring += entries;
++ skb_tab += entries;
++ }
++
++ return 0;
++}
++
++static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
++ unsigned int r)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int m = (1 << port->txq_order) - 1;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int c = txq->cptr;
++ union gmac_txdesc_0 word0;
++ union gmac_txdesc_1 word1;
++ unsigned int hwchksum = 0;
++ unsigned long bytes = 0;
++ struct gmac_txdesc *txd;
++ unsigned short nfrags;
++ unsigned int errs = 0;
++ unsigned int pkts = 0;
++ unsigned int word3;
++ dma_addr_t mapping;
++
++ if (c == r)
++ return;
++
++ while (c != r) {
++ txd = txq->ring + c;
++ word0 = txd->word0;
++ word1 = txd->word1;
++ mapping = txd->word2.buf_adr;
++ word3 = txd->word3.bits32;
++
++ dma_unmap_single(geth->dev, mapping,
++ word0.bits.buffer_size, DMA_TO_DEVICE);
++
++ if (word3 & EOF_BIT)
++ dev_kfree_skb(txq->skb[c]);
++
++ c++;
++ c &= m;
++
++ if (!(word3 & SOF_BIT))
++ continue;
++
++ if (!word0.bits.status_tx_ok) {
++ errs++;
++ continue;
++ }
++
++ pkts++;
++ bytes += txd->word1.bits.byte_count;
++
++ if (word1.bits32 & TSS_CHECKUM_ENABLE)
++ hwchksum++;
++
++ nfrags = word0.bits.desc_count - 1;
++ if (nfrags) {
++ if (nfrags >= TX_MAX_FRAGS)
++ nfrags = TX_MAX_FRAGS - 1;
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->tx_frag_stats[nfrags]++;
++ u64_stats_update_end(&port->ir_stats_syncp);
++ }
++ }
++
++ u64_stats_update_begin(&port->ir_stats_syncp);
++ port->stats.tx_errors += errs;
++ port->stats.tx_packets += pkts;
++ port->stats.tx_bytes += bytes;
++ port->tx_hw_csummed += hwchksum;
++ u64_stats_update_end(&port->ir_stats_syncp);
++
++ txq->cptr = c;
++}
++
++static void gmac_cleanup_txqs(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int n_txq = netdev->num_tx_queues;
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *rwptr_reg;
++ unsigned int r, i;
++
++ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ for (i = 0; i < n_txq; i++) {
++ r = readw(rwptr_reg);
++ rwptr_reg += 2;
++ writew(r, rwptr_reg);
++ rwptr_reg += 2;
++
++ gmac_clean_txq(netdev, port->txq + i, r);
++ }
++ writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
++
++ kfree(port->txq->skb);
++ dma_free_coherent(geth->dev,
++ n_txq * sizeof(*port->txq->ring) << port->txq_order,
++ port->txq->ring, port->txq_dma_base);
++}
++
++static int gmac_setup_rxq(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ struct nontoe_qhdr __iomem *qhdr;
++
++ qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
++ port->rxq_rwptr = &qhdr->word1;
++
++ /* Remap a slew of memory to use for the RX queue */
++ port->rxq_ring = dma_alloc_coherent(geth->dev,
++ sizeof(*port->rxq_ring) << port->rxq_order,
++ &port->rxq_dma_base, GFP_KERNEL);
++ if (!port->rxq_ring)
++ return -ENOMEM;
++ if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
++ dev_warn(geth->dev, "RX queue base it not aligned\n");
++ return -ENOMEM;
++ }
++
++ writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
++ writel(0, port->rxq_rwptr);
++ return 0;
++}
++
++static struct gmac_queue_page *
++gmac_get_queue_page(struct gemini_ethernet *geth,
++ struct gemini_ethernet_port *port,
++ dma_addr_t addr)
++{
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++ int i;
++
++ /* Only look for even pages */
++ mapping = addr & PAGE_MASK;
++
++ if (!geth->freeq_pages) {
++ dev_err(geth->dev, "try to get page with no page list\n");
++ return NULL;
++ }
++
++ /* Look up a ring buffer page from virtual mapping */
++ for (i = 0; i < geth->num_freeq_pages; i++) {
++ gpage = &geth->freeq_pages[i];
++ if (gpage->mapping == mapping)
++ return gpage;
++ }
++
++ return NULL;
++}
++
++static void gmac_cleanup_rxq(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ struct gmac_rxdesc *rxd = port->rxq_ring;
++ static struct gmac_queue_page *gpage;
++ struct nontoe_qhdr __iomem *qhdr;
++ void __iomem *dma_reg;
++ void __iomem *ptr_reg;
++ dma_addr_t mapping;
++ union dma_rwptr rw;
++ unsigned int r, w;
++
++ qhdr = geth->base +
++ TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
++ dma_reg = &qhdr->word0;
++ ptr_reg = &qhdr->word1;
++
++ rw.bits32 = readl(ptr_reg);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++ writew(r, ptr_reg + 2);
++
++ writel(0, dma_reg);
++
++ /* Loop from read pointer to write pointer of the RX queue
++ * and free up all pages by the queue.
++ */
++ while (r != w) {
++ mapping = rxd[r].word2.buf_adr;
++ r++;
++ r &= ((1 << port->rxq_order) - 1);
++
++ if (!mapping)
++ continue;
++
++ /* Freeq pointers are one page off */
++ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
++ if (!gpage) {
++ dev_err(geth->dev, "could not find page\n");
++ continue;
++ }
++ /* Release the RX queue reference to the page */
++ put_page(gpage->page);
++ }
++
++ dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
++ port->rxq_ring, port->rxq_dma_base);
++}
++
++static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
++ int pn)
++{
++ struct gmac_rxdesc *freeq_entry;
++ struct gmac_queue_page *gpage;
++ unsigned int fpp_order;
++ unsigned int frag_len;
++ dma_addr_t mapping;
++ struct page *page;
++ int i;
++
++ /* First allocate and DMA map a single page */
++ page = alloc_page(GFP_ATOMIC);
++ if (!page)
++ return NULL;
++
++ mapping = dma_map_single(geth->dev, page_address(page),
++ PAGE_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(geth->dev, mapping)) {
++ put_page(page);
++ return NULL;
++ }
++
++ /* The assign the page mapping (physical address) to the buffer address
++ * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
++ * 4k), and the default RX frag order is 11 (fragments are up 20 2048
++ * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
++ * each page normally needs two entries in the queue.
++ */
++ frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
++ fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ freeq_entry = geth->freeq_ring + (pn << fpp_order);
++ dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
++ pn, frag_len, (1 << fpp_order), freeq_entry);
++ for (i = (1 << fpp_order); i > 0; i--) {
++ freeq_entry->word2.buf_adr = mapping;
++ freeq_entry++;
++ mapping += frag_len;
++ }
++
++ /* If the freeq entry already has a page mapped, then unmap it. */
++ gpage = &geth->freeq_pages[pn];
++ if (gpage->page) {
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++ /* This should be the last reference to the page so it gets
++ * released
++ */
++ put_page(gpage->page);
++ }
++
++ /* Then put our new mapping into the page table */
++ dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
++ pn, (unsigned int)mapping, page);
++ gpage->mapping = mapping;
++ gpage->page = page;
++
++ return page;
++}
++
++/**
++ * geth_fill_freeq() - Fill the freeq with empty fragments to use
++ * @geth: the ethernet adapter
++ * @refill: whether to reset the queue by filling in all freeq entries or
++ * just refill it, usually the interrupt to refill the queue happens when
++ * the queue is half empty.
++ */
++static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int count = 0;
++ unsigned int pn, epn;
++ unsigned long flags;
++ union dma_rwptr rw;
++ unsigned int m_pn;
++
++ /* Mask for page */
++ m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
++
++ spin_lock_irqsave(&geth->freeq_lock, flags);
++
++ rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
++ pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
++ epn = (rw.bits.rptr >> fpp_order) - 1;
++ epn &= m_pn;
++
++ /* Loop over the freeq ring buffer entries */
++ while (pn != epn) {
++ struct gmac_queue_page *gpage;
++ struct page *page;
++
++ gpage = &geth->freeq_pages[pn];
++ page = gpage->page;
++
++ dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
++ pn, page_ref_count(page), 1 << fpp_order);
++
++ if (page_ref_count(page) > 1) {
++ unsigned int fl = (pn - epn) & m_pn;
++
++ if (fl > 64 >> fpp_order)
++ break;
++
++ page = geth_freeq_alloc_map_page(geth, pn);
++ if (!page)
++ break;
++ }
++
++ /* Add one reference per fragment in the page */
++ page_ref_add(page, 1 << fpp_order);
++ count += 1 << fpp_order;
++ pn++;
++ pn &= m_pn;
++ }
++
++ writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
++
++ spin_unlock_irqrestore(&geth->freeq_lock, flags);
++
++ return count;
++}
++
++static int geth_setup_freeq(struct gemini_ethernet *geth)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int frag_len = 1 << geth->freeq_frag_order;
++ unsigned int len = 1 << geth->freeq_order;
++ unsigned int pages = len >> fpp_order;
++ union queue_threshold qt;
++ union dma_skb_size skbsz;
++ unsigned int filled;
++ unsigned int pn;
++
++ geth->freeq_ring = dma_alloc_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ &geth->freeq_dma_base, GFP_KERNEL);
++ if (!geth->freeq_ring)
++ return -ENOMEM;
++ if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
++ dev_warn(geth->dev, "queue ring base it not aligned\n");
++ goto err_freeq;
++ }
++
++ /* Allocate a mapping to page look-up index */
++ geth->freeq_pages = kzalloc(pages * sizeof(*geth->freeq_pages),
++ GFP_KERNEL);
++ if (!geth->freeq_pages)
++ goto err_freeq;
++ geth->num_freeq_pages = pages;
++
++ dev_info(geth->dev, "allocate %d pages for queue\n", pages);
++ for (pn = 0; pn < pages; pn++)
++ if (!geth_freeq_alloc_map_page(geth, pn))
++ goto err_freeq_alloc;
++
++ filled = geth_fill_freeq(geth, false);
++ if (!filled)
++ goto err_freeq_alloc;
++
++ qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
++ qt.bits.swfq_empty = 32;
++ writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
++
++ skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
++ writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
++ writel(geth->freeq_dma_base | geth->freeq_order,
++ geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++
++ return 0;
++
++err_freeq_alloc:
++ while (pn > 0) {
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++
++ --pn;
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++ gpage = &geth->freeq_pages[pn];
++ put_page(gpage->page);
++ }
++
++ kfree(geth->freeq_pages);
++err_freeq:
++ dma_free_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ geth->freeq_ring, geth->freeq_dma_base);
++ geth->freeq_ring = NULL;
++ return -ENOMEM;
++}
++
++/**
++ * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
++ * @geth: the Gemini global ethernet state
++ */
++static void geth_cleanup_freeq(struct gemini_ethernet *geth)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int frag_len = 1 << geth->freeq_frag_order;
++ unsigned int len = 1 << geth->freeq_order;
++ unsigned int pages = len >> fpp_order;
++ unsigned int pn;
++
++ writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
++ geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
++ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++
++ for (pn = 0; pn < pages; pn++) {
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++
++ gpage = &geth->freeq_pages[pn];
++ while (page_ref_count(gpage->page) > 0)
++ put_page(gpage->page);
++ }
++
++ kfree(geth->freeq_pages);
++
++ dma_free_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ geth->freeq_ring, geth->freeq_dma_base);
++}
++
++/**
++ * geth_resize_freeq() - resize the software queue depth
++ * @port: the port requesting the change
++ *
++ * This gets called at least once during probe() so the device queue gets
++ * "resized" from the hardware defaults. Since both ports/net devices share
++ * the same hardware queue, some synchronization between the ports is
++ * needed.
++ */
++static int geth_resize_freeq(struct gemini_ethernet_port *port)
++{
++ struct gemini_ethernet *geth = port->geth;
++ struct net_device *netdev = port->netdev;
++ struct gemini_ethernet_port *other_port;
++ struct net_device *other_netdev;
++ unsigned int new_size = 0;
++ unsigned int new_order;
++ unsigned long flags;
++ u32 en;
++ int ret;
++
++ if (netdev->dev_id == 0)
++ other_netdev = geth->port1->netdev;
++ else
++ other_netdev = geth->port0->netdev;
++
++ if (other_netdev && netif_running(other_netdev))
++ return -EBUSY;
++
++ new_size = 1 << (port->rxq_order + 1);
++ netdev_dbg(netdev, "port %d size: %d order %d\n",
++ netdev->dev_id,
++ new_size,
++ port->rxq_order);
++ if (other_netdev) {
++ other_port = netdev_priv(other_netdev);
++ new_size += 1 << (other_port->rxq_order + 1);
++ netdev_dbg(other_netdev, "port %d size: %d order %d\n",
++ other_netdev->dev_id,
++ (1 << (other_port->rxq_order + 1)),
++ other_port->rxq_order);
++ }
++
++ new_order = min(15, ilog2(new_size - 1) + 1);
++ dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
++ new_size, new_order);
++ if (geth->freeq_order == new_order)
++ return 0;
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
++ /* Disable the software queue IRQs */
++ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ en &= ~SWFQ_EMPTY_INT_BIT;
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ /* Drop the old queue */
++ if (geth->freeq_ring)
++ geth_cleanup_freeq(geth);
++
++ /* Allocate a new queue with the desired order */
++ geth->freeq_order = new_order;
++ ret = geth_setup_freeq(geth);
++
++ /* Restart the interrupts - NOTE if this is the first resize
++ * after probe(), this is where the interrupts get turned on
++ * in the first place.
++ */
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ en |= SWFQ_EMPTY_INT_BIT;
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ return ret;
++}
++
++static void gmac_tx_irq_enable(struct net_device *netdev,
++ unsigned int txq, int en)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ u32 val, mask;
++
++ netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
++
++ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
++
++ if (en)
++ writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ val = en ? val | mask : val & ~mask;
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++}
++
++static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
++{
++ struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
++
++ gmac_tx_irq_enable(netdev, txq_num, 0);
++ netif_tx_wake_queue(ntxq);
++}
++
++static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
++ struct gmac_txq *txq, unsigned short *desc)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct skb_shared_info *skb_si = skb_shinfo(skb);
++ unsigned short m = (1 << port->txq_order) - 1;
++ short frag, last_frag = skb_si->nr_frags - 1;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int word1, word3, buflen;
++ unsigned short w = *desc;
++ struct gmac_txdesc *txd;
++ skb_frag_t *skb_frag;
++ dma_addr_t mapping;
++ unsigned short mtu;
++ void *buffer;
++
++ mtu = ETH_HLEN;
++ mtu += netdev->mtu;
++ if (skb->protocol == htons(ETH_P_8021Q))
++ mtu += VLAN_HLEN;
++
++ word1 = skb->len;
++ word3 = SOF_BIT;
++
++ if (word1 > mtu) {
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mtu;
++ }
++
++ if (skb->ip_summed != CHECKSUM_NONE) {
++ int tcp = 0;
++
++ if (skb->protocol == htons(ETH_P_IP)) {
++ word1 |= TSS_IP_CHKSUM_BIT;
++ tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
++ } else { /* IPv6 */
++ word1 |= TSS_IPV6_ENABLE_BIT;
++ tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
++ }
++
++ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
++ }
++
++ frag = -1;
++ while (frag <= last_frag) {
++ if (frag == -1) {
++ buffer = skb->data;
++ buflen = skb_headlen(skb);
++ } else {
++ skb_frag = skb_si->frags + frag;
++ buffer = page_address(skb_frag_page(skb_frag)) +
++ skb_frag->page_offset;
++ buflen = skb_frag->size;
++ }
++
++ if (frag == last_frag) {
++ word3 |= EOF_BIT;
++ txq->skb[w] = skb;
++ }
++
++ mapping = dma_map_single(geth->dev, buffer, buflen,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(geth->dev, mapping))
++ goto map_error;
++
++ txd = txq->ring + w;
++ txd->word0.bits32 = buflen;
++ txd->word1.bits32 = word1;
++ txd->word2.buf_adr = mapping;
++ txd->word3.bits32 = word3;
++
++ word3 &= MTU_SIZE_BIT_MASK;
++ w++;
++ w &= m;
++ frag++;
++ }
++
++ *desc = w;
++ return 0;
++
++map_error:
++ while (w != *desc) {
++ w--;
++ w &= m;
++
++ dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
++ txq->ring[w].word0.bits.buffer_size,
++ DMA_TO_DEVICE);
++ }
++ return -ENOMEM;
++}
++
++static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned short m = (1 << port->txq_order) - 1;
++ struct netdev_queue *ntxq;
++ unsigned short r, w, d;
++ void __iomem *ptr_reg;
++ struct gmac_txq *txq;
++ int txq_num, nfrags;
++ union dma_rwptr rw;
++
++ SKB_FRAG_ASSERT(skb);
++
++ if (skb->len >= 0x10000)
++ goto out_drop_free;
++
++ txq_num = skb_get_queue_mapping(skb);
++ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
++ txq = &port->txq[txq_num];
++ ntxq = netdev_get_tx_queue(netdev, txq_num);
++ nfrags = skb_shinfo(skb)->nr_frags;
++
++ rw.bits32 = readl(ptr_reg);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++
++ d = txq->cptr - w - 1;
++ d &= m;
++
++ if (d < nfrags + 2) {
++ gmac_clean_txq(netdev, txq, r);
++ d = txq->cptr - w - 1;
++ d &= m;
++
++ if (d < nfrags + 2) {
++ netif_tx_stop_queue(ntxq);
++
++ d = txq->cptr + nfrags + 16;
++ d &= m;
++ txq->ring[d].word3.bits.eofie = 1;
++ gmac_tx_irq_enable(netdev, txq_num, 1);
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ netdev->stats.tx_fifo_errors++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++ return NETDEV_TX_BUSY;
++ }
++ }
++
++ if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
++ if (skb_linearize(skb))
++ goto out_drop;
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->tx_frags_linearized++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++
++ if (gmac_map_tx_bufs(netdev, skb, txq, &w))
++ goto out_drop_free;
++ }
++
++ writew(w, ptr_reg + 2);
++
++ gmac_clean_txq(netdev, txq, r);
++ return NETDEV_TX_OK;
++
++out_drop_free:
++ dev_kfree_skb(skb);
++out_drop:
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->stats.tx_dropped++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++ return NETDEV_TX_OK;
++}
++
++static void gmac_tx_timeout(struct net_device *netdev)
++{
++ netdev_err(netdev, "Tx timeout\n");
++ gmac_dump_dma_state(netdev);
++}
++
++static void gmac_enable_irq(struct net_device *netdev, int enable)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++ u32 val, mask;
++
++ netdev_info(netdev, "%s device %d %s\n", __func__,
++ netdev->dev_id, enable ? "enable" : "disable");
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
++ mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++
++ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++
++ mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++ u32 val, mask;
++
++ netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
++ enable ? "enable" : "disable");
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
++ union gmac_rxdesc_0 word0,
++ unsigned int frame_len)
++{
++ unsigned int rx_csum = word0.bits.chksum_status;
++ unsigned int rx_status = word0.bits.status;
++ struct sk_buff *skb = NULL;
++
++ port->rx_stats[rx_status]++;
++ port->rx_csum_stats[rx_csum]++;
++
++ if (word0.bits.derr || word0.bits.perr ||
++ rx_status || frame_len < ETH_ZLEN ||
++ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
++ port->stats.rx_errors++;
++
++ if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
++ port->stats.rx_length_errors++;
++ if (RX_ERROR_OVER(rx_status))
++ port->stats.rx_over_errors++;
++ if (RX_ERROR_CRC(rx_status))
++ port->stats.rx_crc_errors++;
++ if (RX_ERROR_FRAME(rx_status))
++ port->stats.rx_frame_errors++;
++ return NULL;
++ }
++
++ skb = napi_get_frags(&port->napi);
++ if (!skb)
++ goto update_exit;
++
++ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++
++update_exit:
++ port->stats.rx_bytes += frame_len;
++ port->stats.rx_packets++;
++ return skb;
++}
++
++static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned short m = (1 << port->rxq_order) - 1;
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *ptr_reg = port->rxq_rwptr;
++ unsigned int frame_len, frag_len;
++ struct gmac_rxdesc *rx = NULL;
++ struct gmac_queue_page *gpage;
++ static struct sk_buff *skb;
++ union gmac_rxdesc_0 word0;
++ union gmac_rxdesc_1 word1;
++ union gmac_rxdesc_3 word3;
++ struct page *page = NULL;
++ unsigned int page_offs;
++ unsigned short r, w;
++ union dma_rwptr rw;
++ dma_addr_t mapping;
++ int frag_nr = 0;
++
++ rw.bits32 = readl(ptr_reg);
++ /* Reset interrupt as all packages until here are taken into account */
++ writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
++ geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++
++ while (budget && w != r) {
++ rx = port->rxq_ring + r;
++ word0 = rx->word0;
++ word1 = rx->word1;
++ mapping = rx->word2.buf_adr;
++ word3 = rx->word3;
++
++ r++;
++ r &= m;
++
++ frag_len = word0.bits.buffer_size;
++ frame_len = word1.bits.byte_count;
++ page_offs = mapping & ~PAGE_MASK;
++
++ if (!mapping) {
++ netdev_err(netdev,
++ "rxq[%u]: HW BUG: zero DMA desc\n", r);
++ goto err_drop;
++ }
++
++ /* Freeq pointers are one page off */
++ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
++ if (!gpage) {
++ dev_err(geth->dev, "could not find mapping\n");
++ continue;
++ }
++ page = gpage->page;
++
++ if (word3.bits32 & SOF_BIT) {
++ if (skb) {
++ napi_free_frags(&port->napi);
++ port->stats.rx_dropped++;
++ }
++
++ skb = gmac_skb_if_good_frame(port, word0, frame_len);
++ if (!skb)
++ goto err_drop;
++
++ page_offs += NET_IP_ALIGN;
++ frag_len -= NET_IP_ALIGN;
++ frag_nr = 0;
++
++ } else if (!skb) {
++ put_page(page);
++ continue;
++ }
++
++ if (word3.bits32 & EOF_BIT)
++ frag_len = frame_len - skb->len;
++
++ /* append page frag to skb */
++ if (frag_nr == MAX_SKB_FRAGS)
++ goto err_drop;
++
++ if (frag_len == 0)
++ netdev_err(netdev, "Received fragment with len = 0\n");
++
++ skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
++ skb->len += frag_len;
++ skb->data_len += frag_len;
++ skb->truesize += frag_len;
++ frag_nr++;
++
++ if (word3.bits32 & EOF_BIT) {
++ napi_gro_frags(&port->napi);
++ skb = NULL;
++ --budget;
++ }
++ continue;
++
++err_drop:
++ if (skb) {
++ napi_free_frags(&port->napi);
++ skb = NULL;
++ }
++
++ if (mapping)
++ put_page(page);
++
++ port->stats.rx_dropped++;
++ }
++
++ writew(r, ptr_reg);
++ return budget;
++}
++
++static int gmac_napi_poll(struct napi_struct *napi, int budget)
++{
++ struct gemini_ethernet_port *port = netdev_priv(napi->dev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int freeq_threshold;
++ unsigned int received;
++
++ freeq_threshold = 1 << (geth->freeq_order - 1);
++ u64_stats_update_begin(&port->rx_stats_syncp);
++
++ received = gmac_rx(napi->dev, budget);
++ if (received < budget) {
++ napi_gro_flush(napi, false);
++ napi_complete_done(napi, received);
++ gmac_enable_rx_irq(napi->dev, 1);
++ ++port->rx_napi_exits;
++ }
++
++ port->freeq_refill += (budget - received);
++ if (port->freeq_refill > freeq_threshold) {
++ port->freeq_refill -= freeq_threshold;
++ geth_fill_freeq(geth, true);
++ }
++
++ u64_stats_update_end(&port->rx_stats_syncp);
++ return received;
++}
++
++static void gmac_dump_dma_state(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *ptr_reg;
++ u32 reg[5];
++
++ /* Interrupt status */
++ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
++ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
++ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3], reg[4]);
++
++ /* Interrupt enable */
++ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
++ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
++ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3], reg[4]);
++
++ /* RX DMA status */
++ reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
++ reg[2] = GET_RPTR(port->rxq_rwptr);
++ reg[3] = GET_WPTR(port->rxq_rwptr);
++ netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
++ reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
++ reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
++ netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ /* TX DMA status */
++ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
++ reg[2] = GET_RPTR(ptr_reg);
++ reg[3] = GET_WPTR(ptr_reg);
++ netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
++ reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
++ reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
++ netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ /* FREE queues status */
++ ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
++
++ reg[0] = GET_RPTR(ptr_reg);
++ reg[1] = GET_WPTR(ptr_reg);
++
++ ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
++
++ reg[2] = GET_RPTR(ptr_reg);
++ reg[3] = GET_WPTR(ptr_reg);
++ netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++}
++
++static void gmac_update_hw_stats(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int rx_discards, rx_mcast, rx_bcast;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ u64_stats_update_begin(&port->ir_stats_syncp);
++
++ rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
++ port->hw_stats[0] += rx_discards;
++ port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
++ rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
++ port->hw_stats[2] += rx_mcast;
++ rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
++ port->hw_stats[3] += rx_bcast;
++ port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
++ port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
++
++ port->stats.rx_missed_errors += rx_discards;
++ port->stats.multicast += rx_mcast;
++ port->stats.multicast += rx_bcast;
++
++ writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
++ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ u64_stats_update_end(&port->ir_stats_syncp);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++/**
++ * gmac_get_intr_flags() - get interrupt status flags for a port from
++ * @netdev: the net device for the port to get flags from
++ * @i: the interrupt status register 0..4
++ */
++static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *irqif_reg, *irqen_reg;
++ unsigned int offs, val;
++
++ /* Calculate the offset using the stride of the status registers */
++ offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
++ GLOBAL_INTERRUPT_STATUS_0_REG);
++
++ irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
++ irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
++
++ val = readl(irqif_reg) & readl(irqen_reg);
++ return val;
++}
++
++static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
++{
++ struct gemini_ethernet_port *port =
++ container_of(timer, struct gemini_ethernet_port,
++ rx_coalesce_timer);
++
++ napi_schedule(&port->napi);
++ return HRTIMER_NORESTART;
++}
++
++static irqreturn_t gmac_irq(int irq, void *data)
++{
++ struct gemini_ethernet_port *port;
++ struct net_device *netdev = data;
++ struct gemini_ethernet *geth;
++ u32 val, orr = 0;
++
++ port = netdev_priv(netdev);
++ geth = port->geth;
++
++ val = gmac_get_intr_flags(netdev, 0);
++ orr |= val;
++
++ if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
++ /* Oh, crap */
++ netdev_err(netdev, "hw failure/sw bug\n");
++ gmac_dump_dma_state(netdev);
++
++ /* don't know how to recover, just reduce losses */
++ gmac_enable_irq(netdev, 0);
++ return IRQ_HANDLED;
++ }
++
++ if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
++ gmac_tx_irq(netdev, 0);
++
++ val = gmac_get_intr_flags(netdev, 1);
++ orr |= val;
++
++ if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
++ gmac_enable_rx_irq(netdev, 0);
++
++ if (!port->rx_coalesce_nsecs) {
++ napi_schedule(&port->napi);
++ } else {
++ ktime_t ktime;
++
++ ktime = ktime_set(0, port->rx_coalesce_nsecs);
++ hrtimer_start(&port->rx_coalesce_timer, ktime,
++ HRTIMER_MODE_REL);
++ }
++ }
++
++ val = gmac_get_intr_flags(netdev, 4);
++ orr |= val;
++
++ if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
++ gmac_update_hw_stats(netdev);
++
++ if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
++ writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
++ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ spin_lock(&geth->irq_lock);
++ u64_stats_update_begin(&port->ir_stats_syncp);
++ ++port->stats.rx_fifo_errors;
++ u64_stats_update_end(&port->ir_stats_syncp);
++ spin_unlock(&geth->irq_lock);
++ }
++
++ return orr ? IRQ_HANDLED : IRQ_NONE;
++}
++
++static void gmac_start_dma(struct gemini_ethernet_port *port)
++{
++ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
++ union gmac_dma_ctrl dma_ctrl;
++
++ dma_ctrl.bits32 = readl(dma_ctrl_reg);
++ dma_ctrl.bits.rd_enable = 1;
++ dma_ctrl.bits.td_enable = 1;
++ dma_ctrl.bits.loopback = 0;
++ dma_ctrl.bits.drop_small_ack = 0;
++ dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
++ dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
++ dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
++ dma_ctrl.bits.rd_bus = HSIZE_8;
++ dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
++ dma_ctrl.bits.td_burst_size = HBURST_INCR8;
++ dma_ctrl.bits.td_bus = HSIZE_8;
++
++ writel(dma_ctrl.bits32, dma_ctrl_reg);
++}
++
++static void gmac_stop_dma(struct gemini_ethernet_port *port)
++{
++ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
++ union gmac_dma_ctrl dma_ctrl;
++
++ dma_ctrl.bits32 = readl(dma_ctrl_reg);
++ dma_ctrl.bits.rd_enable = 0;
++ dma_ctrl.bits.td_enable = 0;
++ writel(dma_ctrl.bits32, dma_ctrl_reg);
++}
++
++static int gmac_open(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int err;
++
++ if (!netdev->phydev) {
++ err = gmac_setup_phy(netdev);
++ if (err) {
++ netif_err(port, ifup, netdev,
++ "PHY init failed: %d\n", err);
++ return err;
++ }
++ }
++
++ err = request_irq(netdev->irq, gmac_irq,
++ IRQF_SHARED, netdev->name, netdev);
++ if (err) {
++ netdev_err(netdev, "no IRQ\n");
++ return err;
++ }
++
++ netif_carrier_off(netdev);
++ phy_start(netdev->phydev);
++
++ err = geth_resize_freeq(port);
++ if (err) {
++ netdev_err(netdev, "could not resize freeq\n");
++ goto err_stop_phy;
++ }
++
++ err = gmac_setup_rxq(netdev);
++ if (err) {
++ netdev_err(netdev, "could not setup RXQ\n");
++ goto err_stop_phy;
++ }
++
++ err = gmac_setup_txqs(netdev);
++ if (err) {
++ netdev_err(netdev, "could not setup TXQs\n");
++ gmac_cleanup_rxq(netdev);
++ goto err_stop_phy;
++ }
++
++ napi_enable(&port->napi);
++
++ gmac_start_dma(port);
++ gmac_enable_irq(netdev, 1);
++ gmac_enable_tx_rx(netdev);
++ netif_tx_start_all_queues(netdev);
++
++ hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
++
++ netdev_info(netdev, "opened\n");
++
++ return 0;
++
++err_stop_phy:
++ phy_stop(netdev->phydev);
++ free_irq(netdev->irq, netdev);
++ return err;
++}
++
++static int gmac_stop(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ hrtimer_cancel(&port->rx_coalesce_timer);
++ netif_tx_stop_all_queues(netdev);
++ gmac_disable_tx_rx(netdev);
++ gmac_stop_dma(port);
++ napi_disable(&port->napi);
++
++ gmac_enable_irq(netdev, 0);
++ gmac_cleanup_rxq(netdev);
++ gmac_cleanup_txqs(netdev);
++
++ phy_stop(netdev->phydev);
++ free_irq(netdev->irq, netdev);
++
++ gmac_update_hw_stats(netdev);
++ return 0;
++}
++
++static void gmac_set_rx_mode(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_rx_fltr filter = { .bits = {
++ .broadcast = 1,
++ .multicast = 1,
++ .unicast = 1,
++ } };
++ struct netdev_hw_addr *ha;
++ unsigned int bit_nr;
++ u32 mc_filter[2];
++
++ mc_filter[1] = 0;
++ mc_filter[0] = 0;
++
++ if (netdev->flags & IFF_PROMISC) {
++ filter.bits.error = 1;
++ filter.bits.promiscuous = 1;
++ mc_filter[1] = ~0;
++ mc_filter[0] = ~0;
++ } else if (netdev->flags & IFF_ALLMULTI) {
++ mc_filter[1] = ~0;
++ mc_filter[0] = ~0;
++ } else {
++ netdev_for_each_mc_addr(ha, netdev) {
++ bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
++ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
++ }
++ }
++
++ writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
++ writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
++ writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
++}
++
++static void gmac_write_mac_address(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ __le32 addr[3];
++
++ memset(addr, 0, sizeof(addr));
++ memcpy(addr, netdev->dev_addr, ETH_ALEN);
++
++ writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
++ writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
++ writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
++}
++
++static int gmac_set_mac_address(struct net_device *netdev, void *addr)
++{
++ struct sockaddr *sa = addr;
++
++ memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
++ gmac_write_mac_address(netdev);
++
++ return 0;
++}
++
++static void gmac_clear_hw_stats(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ readl(port->gmac_base + GMAC_IN_DISCARDS);
++ readl(port->gmac_base + GMAC_IN_ERRORS);
++ readl(port->gmac_base + GMAC_IN_MCAST);
++ readl(port->gmac_base + GMAC_IN_BCAST);
++ readl(port->gmac_base + GMAC_IN_MAC1);
++ readl(port->gmac_base + GMAC_IN_MAC2);
++}
++
++static void gmac_get_stats64(struct net_device *netdev,
++ struct rtnl_link_stats64 *stats)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int start;
++
++ gmac_update_hw_stats(netdev);
++
++ /* Racing with RX NAPI */
++ do {
++ start = u64_stats_fetch_begin(&port->rx_stats_syncp);
++
++ stats->rx_packets = port->stats.rx_packets;
++ stats->rx_bytes = port->stats.rx_bytes;
++ stats->rx_errors = port->stats.rx_errors;
++ stats->rx_dropped = port->stats.rx_dropped;
++
++ stats->rx_length_errors = port->stats.rx_length_errors;
++ stats->rx_over_errors = port->stats.rx_over_errors;
++ stats->rx_crc_errors = port->stats.rx_crc_errors;
++ stats->rx_frame_errors = port->stats.rx_frame_errors;
++
++ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
++
++ /* Racing with MIB and TX completion interrupts */
++ do {
++ start = u64_stats_fetch_begin(&port->ir_stats_syncp);
++
++ stats->tx_errors = port->stats.tx_errors;
++ stats->tx_packets = port->stats.tx_packets;
++ stats->tx_bytes = port->stats.tx_bytes;
++
++ stats->multicast = port->stats.multicast;
++ stats->rx_missed_errors = port->stats.rx_missed_errors;
++ stats->rx_fifo_errors = port->stats.rx_fifo_errors;
++
++ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
++
++ /* Racing with hard_start_xmit */
++ do {
++ start = u64_stats_fetch_begin(&port->tx_stats_syncp);
++
++ stats->tx_dropped = port->stats.tx_dropped;
++
++ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
++
++ stats->rx_dropped += stats->rx_missed_errors;
++}
++
++static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
++{
++ int max_len = gmac_pick_rx_max_len(new_mtu);
++
++ if (max_len < 0)
++ return -EINVAL;
++
++ gmac_disable_tx_rx(netdev);
++
++ netdev->mtu = new_mtu;
++ gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
++ CONFIG0_MAXLEN_MASK);
++
++ netdev_update_features(netdev);
++
++ gmac_enable_tx_rx(netdev);
++
++ return 0;
++}
++
++static netdev_features_t gmac_fix_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
++ features &= ~GMAC_OFFLOAD_FEATURES;
++
++ return features;
++}
++
++static int gmac_set_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int enable = features & NETIF_F_RXCSUM;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++ return 0;
++}
++
++static int gmac_get_sset_count(struct net_device *netdev, int sset)
++{
++ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
++}
++
++static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
++{
++ if (stringset != ETH_SS_STATS)
++ return;
++
++ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
++}
++
++static void gmac_get_ethtool_stats(struct net_device *netdev,
++ struct ethtool_stats *estats, u64 *values)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int start;
++ u64 *p;
++ int i;
++
++ gmac_update_hw_stats(netdev);
++
++ /* Racing with MIB interrupt */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->ir_stats_syncp);
++
++ for (i = 0; i < RX_STATS_NUM; i++)
++ *p++ = port->hw_stats[i];
++
++ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
++ values = p;
++
++ /* Racing with RX NAPI */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->rx_stats_syncp);
++
++ for (i = 0; i < RX_STATUS_NUM; i++)
++ *p++ = port->rx_stats[i];
++ for (i = 0; i < RX_CHKSUM_NUM; i++)
++ *p++ = port->rx_csum_stats[i];
++ *p++ = port->rx_napi_exits;
++
++ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
++ values = p;
++
++ /* Racing with TX start_xmit */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->tx_stats_syncp);
++
++ for (i = 0; i < TX_MAX_FRAGS; i++) {
++ *values++ = port->tx_frag_stats[i];
++ port->tx_frag_stats[i] = 0;
++ }
++ *values++ = port->tx_frags_linearized;
++ *values++ = port->tx_hw_csummed;
++
++ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
++}
++
++static int gmac_get_ksettings(struct net_device *netdev,
++ struct ethtool_link_ksettings *cmd)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ phy_ethtool_ksettings_get(netdev->phydev, cmd);
++
++ return 0;
++}
++
++static int gmac_set_ksettings(struct net_device *netdev,
++ const struct ethtool_link_ksettings *cmd)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ return phy_ethtool_ksettings_set(netdev->phydev, cmd);
++}
++
++static int gmac_nway_reset(struct net_device *netdev)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ return phy_start_aneg(netdev->phydev);
++}
++
++static void gmac_get_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pparam)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0;
++
++ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++
++ pparam->rx_pause = config0.bits.rx_fc_en;
++ pparam->tx_pause = config0.bits.tx_fc_en;
++ pparam->autoneg = true;
++}
++
++static void gmac_get_ringparam(struct net_device *netdev,
++ struct ethtool_ringparam *rp)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0;
++
++ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++
++ rp->rx_max_pending = 1 << 15;
++ rp->rx_mini_max_pending = 0;
++ rp->rx_jumbo_max_pending = 0;
++ rp->tx_max_pending = 1 << 15;
++
++ rp->rx_pending = 1 << port->rxq_order;
++ rp->rx_mini_pending = 0;
++ rp->rx_jumbo_pending = 0;
++ rp->tx_pending = 1 << port->txq_order;
++}
++
++static int gmac_set_ringparam(struct net_device *netdev,
++ struct ethtool_ringparam *rp)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int err = 0;
++
++ if (netif_running(netdev))
++ return -EBUSY;
++
++ if (rp->rx_pending) {
++ port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
++ err = geth_resize_freeq(port);
++ }
++ if (rp->tx_pending) {
++ port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
++ port->irq_every_tx_packets = 1 << (port->txq_order - 2);
++ }
++
++ return err;
++}
++
++static int gmac_get_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ecmd)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ ecmd->rx_max_coalesced_frames = 1;
++ ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
++ ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
++
++ return 0;
++}
++
++static int gmac_set_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ecmd)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ if (ecmd->tx_max_coalesced_frames < 1)
++ return -EINVAL;
++ if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
++ return -EINVAL;
++
++ port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
++ port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
++
++ return 0;
++}
++
++static u32 gmac_get_msglevel(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ return port->msg_enable;
++}
++
++static void gmac_set_msglevel(struct net_device *netdev, u32 level)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ port->msg_enable = level;
++}
++
++static void gmac_get_drvinfo(struct net_device *netdev,
++ struct ethtool_drvinfo *info)
++{
++ strcpy(info->driver, DRV_NAME);
++ strcpy(info->version, DRV_VERSION);
++ strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
++}
++
++static const struct net_device_ops gmac_351x_ops = {
++ .ndo_init = gmac_init,
++ .ndo_uninit = gmac_uninit,
++ .ndo_open = gmac_open,
++ .ndo_stop = gmac_stop,
++ .ndo_start_xmit = gmac_start_xmit,
++ .ndo_tx_timeout = gmac_tx_timeout,
++ .ndo_set_rx_mode = gmac_set_rx_mode,
++ .ndo_set_mac_address = gmac_set_mac_address,
++ .ndo_get_stats64 = gmac_get_stats64,
++ .ndo_change_mtu = gmac_change_mtu,
++ .ndo_fix_features = gmac_fix_features,
++ .ndo_set_features = gmac_set_features,
++};
++
++static const struct ethtool_ops gmac_351x_ethtool_ops = {
++ .get_sset_count = gmac_get_sset_count,
++ .get_strings = gmac_get_strings,
++ .get_ethtool_stats = gmac_get_ethtool_stats,
++ .get_link = ethtool_op_get_link,
++ .get_link_ksettings = gmac_get_ksettings,
++ .set_link_ksettings = gmac_set_ksettings,
++ .nway_reset = gmac_nway_reset,
++ .get_pauseparam = gmac_get_pauseparam,
++ .get_ringparam = gmac_get_ringparam,
++ .set_ringparam = gmac_set_ringparam,
++ .get_coalesce = gmac_get_coalesce,
++ .set_coalesce = gmac_set_coalesce,
++ .get_msglevel = gmac_get_msglevel,
++ .set_msglevel = gmac_set_msglevel,
++ .get_drvinfo = gmac_get_drvinfo,
++};
++
++static irqreturn_t gemini_port_irq_thread(int irq, void *data)
++{
++ unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
++ struct gemini_ethernet_port *port = data;
++ struct gemini_ethernet *geth;
++ unsigned long flags;
++
++ geth = port->geth;
++ /* The queue is half empty so refill it */
++ geth_fill_freeq(geth, true);
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ /* ACK queue interrupt */
++ writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ /* Enable queue interrupt again */
++ irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t gemini_port_irq(int irq, void *data)
++{
++ struct gemini_ethernet_port *port = data;
++ struct gemini_ethernet *geth;
++ irqreturn_t ret = IRQ_NONE;
++ u32 val, en;
++
++ geth = port->geth;
++ spin_lock(&geth->irq_lock);
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ if (val & en & SWFQ_EMPTY_INT_BIT) {
++ /* Disable the queue empty interrupt while we work on
++ * processing the queue. Also disable overrun interrupts
++ * as there is not much we can do about it here.
++ */
++ en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
++ | GMAC1_RX_OVERRUN_INT_BIT);
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ ret = IRQ_WAKE_THREAD;
++ }
++
++ spin_unlock(&geth->irq_lock);
++
++ return ret;
++}
++
++static void gemini_port_remove(struct gemini_ethernet_port *port)
++{
++ if (port->netdev)
++ unregister_netdev(port->netdev);
++ clk_disable_unprepare(port->pclk);
++ geth_cleanup_freeq(port->geth);
++}
++
++static void gemini_ethernet_init(struct gemini_ethernet *geth)
++{
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ /* Interrupt config:
++ *
++ * GMAC0 intr bits ------> int0 ----> eth0
++ * GMAC1 intr bits ------> int1 ----> eth1
++ * TOE intr -------------> int1 ----> eth1
++ * Classification Intr --> int0 ----> eth0
++ * Default Q0 -----------> int0 ----> eth0
++ * Default Q1 -----------> int1 ----> eth1
++ * FreeQ intr -----------> int1 ----> eth1
++ */
++ writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
++ writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
++ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
++ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
++ writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
++
++ /* edge-triggered interrupts packed to level-triggered one... */
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ /* Set up queue */
++ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++ writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
++ writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
++ writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
++
++ geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
++ /* This makes the queue resize on probe() so that we
++ * set up and enable the queue IRQ. FIXME: fragile.
++ */
++ geth->freeq_order = 1;
++}
++
++static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
++{
++ port->mac_addr[0] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
++ port->mac_addr[1] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
++ port->mac_addr[2] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
++}
++
++static int gemini_ethernet_port_probe(struct platform_device *pdev)
++{
++ char *port_names[2] = { "ethernet0", "ethernet1" };
++ struct gemini_ethernet_port *port;
++ struct device *dev = &pdev->dev;
++ struct gemini_ethernet *geth;
++ struct net_device *netdev;
++ struct resource *gmacres;
++ struct resource *dmares;
++ struct device *parent;
++ unsigned int id;
++ int irq;
++ int ret;
++
++ parent = dev->parent;
++ geth = dev_get_drvdata(parent);
++
++ if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
++ id = 0;
++ else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
++ id = 1;
++ else
++ return -ENODEV;
++
++ dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
++
++ netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
++ if (!netdev) {
++ dev_err(dev, "Can't allocate ethernet device #%d\n", id);
++ return -ENOMEM;
++ }
++
++ port = netdev_priv(netdev);
++ SET_NETDEV_DEV(netdev, dev);
++ port->netdev = netdev;
++ port->id = id;
++ port->geth = geth;
++ port->dev = dev;
++
++ /* DMA memory */
++ dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!dmares) {
++ dev_err(dev, "no DMA resource\n");
++ return -ENODEV;
++ }
++ port->dma_base = devm_ioremap_resource(dev, dmares);
++ if (IS_ERR(port->dma_base))
++ return PTR_ERR(port->dma_base);
++
++ /* GMAC config memory */
++ gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!gmacres) {
++ dev_err(dev, "no GMAC resource\n");
++ return -ENODEV;
++ }
++ port->gmac_base = devm_ioremap_resource(dev, gmacres);
++ if (IS_ERR(port->gmac_base))
++ return PTR_ERR(port->gmac_base);
++
++ /* Interrupt */
++ irq = platform_get_irq(pdev, 0);
++ if (irq <= 0) {
++ dev_err(dev, "no IRQ\n");
++ return irq ? irq : -ENODEV;
++ }
++ port->irq = irq;
++
++ /* Clock the port */
++ port->pclk = devm_clk_get(dev, "PCLK");
++ if (IS_ERR(port->pclk)) {
++ dev_err(dev, "no PCLK\n");
++ return PTR_ERR(port->pclk);
++ }
++ ret = clk_prepare_enable(port->pclk);
++ if (ret)
++ return ret;
++
++ /* Maybe there is a nice ethernet address we should use */
++ gemini_port_save_mac_addr(port);
++
++ /* Reset the port */
++ port->reset = devm_reset_control_get_exclusive(dev, NULL);
++ if (IS_ERR(port->reset)) {
++ dev_err(dev, "no reset\n");
++ return PTR_ERR(port->reset);
++ }
++ reset_control_reset(port->reset);
++ usleep_range(100, 500);
++
++ /* Assign pointer in the main state container */
++ if (!id)
++ geth->port0 = port;
++ else
++ geth->port1 = port;
++ platform_set_drvdata(pdev, port);
++
++ /* Set up and register the netdev */
++ netdev->dev_id = port->id;
++ netdev->irq = irq;
++ netdev->netdev_ops = &gmac_351x_ops;
++ netdev->ethtool_ops = &gmac_351x_ethtool_ops;
++
++ spin_lock_init(&port->config_lock);
++ gmac_clear_hw_stats(netdev);
++
++ netdev->hw_features = GMAC_OFFLOAD_FEATURES;
++ netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
++
++ port->freeq_refill = 0;
++ netif_napi_add(netdev, &port->napi, gmac_napi_poll,
++ DEFAULT_NAPI_WEIGHT);
++
++ if (is_valid_ether_addr((void *)port->mac_addr)) {
++ memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
++ } else {
++ dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
++ port->mac_addr[0], port->mac_addr[1],
++ port->mac_addr[2]);
++ dev_info(dev, "using a random ethernet address\n");
++ random_ether_addr(netdev->dev_addr);
++ }
++ gmac_write_mac_address(netdev);
++
++ ret = devm_request_threaded_irq(port->dev,
++ port->irq,
++ gemini_port_irq,
++ gemini_port_irq_thread,
++ IRQF_SHARED,
++ port_names[port->id],
++ port);
++ if (ret)
++ return ret;
++
++ ret = register_netdev(netdev);
++ if (!ret) {
++ netdev_info(netdev,
++ "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
++ port->irq, &dmares->start,
++ &gmacres->start);
++ ret = gmac_setup_phy(netdev);
++ if (ret)
++ netdev_info(netdev,
++ "PHY init failed, deferring to ifup time\n");
++ return 0;
++ }
++
++ port->netdev = NULL;
++ free_netdev(netdev);
++ return ret;
++}
++
++static int gemini_ethernet_port_remove(struct platform_device *pdev)
++{
++ struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
++
++ gemini_port_remove(port);
++ return 0;
++}
++
++static const struct of_device_id gemini_ethernet_port_of_match[] = {
++ {
++ .compatible = "cortina,gemini-ethernet-port",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
++
++static struct platform_driver gemini_ethernet_port_driver = {
++ .driver = {
++ .name = "gemini-ethernet-port",
++ .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
++ },
++ .probe = gemini_ethernet_port_probe,
++ .remove = gemini_ethernet_port_remove,
++};
++
++static int gemini_ethernet_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct gemini_ethernet *geth;
++ unsigned int retry = 5;
++ struct resource *res;
++ u32 val;
++
++ /* Global registers */
++ geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
++ if (!geth)
++ return -ENOMEM;
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++ geth->base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(geth->base))
++ return PTR_ERR(geth->base);
++ geth->dev = dev;
++
++ /* Wait for ports to stabilize */
++ do {
++ udelay(2);
++ val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
++ barrier();
++ } while (!val && --retry);
++ if (!retry) {
++ dev_err(dev, "failed to reset ethernet\n");
++ return -EIO;
++ }
++ dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
++ (val >> 4) & 0xFFFU, val & 0xFU);
++
++ spin_lock_init(&geth->irq_lock);
++ spin_lock_init(&geth->freeq_lock);
++ gemini_ethernet_init(geth);
++
++ /* The children will use this */
++ platform_set_drvdata(pdev, geth);
++
++ /* Spawn child devices for the two ports */
++ return devm_of_platform_populate(dev);
++}
++
++static int gemini_ethernet_remove(struct platform_device *pdev)
++{
++ struct gemini_ethernet *geth = platform_get_drvdata(pdev);
++
++ gemini_ethernet_init(geth);
++ geth_cleanup_freeq(geth);
++
++ return 0;
++}
++
++static const struct of_device_id gemini_ethernet_of_match[] = {
++ {
++ .compatible = "cortina,gemini-ethernet",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
++
++static struct platform_driver gemini_ethernet_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .of_match_table = of_match_ptr(gemini_ethernet_of_match),
++ },
++ .probe = gemini_ethernet_probe,
++ .remove = gemini_ethernet_remove,
++};
++
++static int __init gemini_ethernet_module_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&gemini_ethernet_port_driver);
++ if (ret)
++ return ret;
++
++ ret = platform_driver_register(&gemini_ethernet_driver);
++ if (ret) {
++ platform_driver_unregister(&gemini_ethernet_port_driver);
++ return ret;
++ }
++
++ return 0;
++}
++module_init(gemini_ethernet_module_init);
++
++static void __exit gemini_ethernet_module_exit(void)
++{
++ platform_driver_unregister(&gemini_ethernet_driver);
++ platform_driver_unregister(&gemini_ethernet_port_driver);
++}
++module_exit(gemini_ethernet_module_exit);
++
++MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
++MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/gemini.h
+@@ -0,0 +1,958 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Register definitions for Gemini GMAC Ethernet device driver
++ *
++ * Copyright (C) 2006 Storlink, Corp.
++ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
++ * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
++ * Copytight (C) 2017 Linus Walleij <linus.walleij@linaro.org>
++ */
++#ifndef _GEMINI_ETHERNET_H
++#define _GEMINI_ETHERNET_H
++
++#include <linux/bitops.h>
++
++/* Base Registers */
++#define TOE_NONTOE_QUE_HDR_BASE 0x2000
++#define TOE_TOE_QUE_HDR_BASE 0x3000
++
++/* Queue ID */
++#define TOE_SW_FREE_QID 0x00
++#define TOE_HW_FREE_QID 0x01
++#define TOE_GMAC0_SW_TXQ0_QID 0x02
++#define TOE_GMAC0_SW_TXQ1_QID 0x03
++#define TOE_GMAC0_SW_TXQ2_QID 0x04
++#define TOE_GMAC0_SW_TXQ3_QID 0x05
++#define TOE_GMAC0_SW_TXQ4_QID 0x06
++#define TOE_GMAC0_SW_TXQ5_QID 0x07
++#define TOE_GMAC0_HW_TXQ0_QID 0x08
++#define TOE_GMAC0_HW_TXQ1_QID 0x09
++#define TOE_GMAC0_HW_TXQ2_QID 0x0A
++#define TOE_GMAC0_HW_TXQ3_QID 0x0B
++#define TOE_GMAC1_SW_TXQ0_QID 0x12
++#define TOE_GMAC1_SW_TXQ1_QID 0x13
++#define TOE_GMAC1_SW_TXQ2_QID 0x14
++#define TOE_GMAC1_SW_TXQ3_QID 0x15
++#define TOE_GMAC1_SW_TXQ4_QID 0x16
++#define TOE_GMAC1_SW_TXQ5_QID 0x17
++#define TOE_GMAC1_HW_TXQ0_QID 0x18
++#define TOE_GMAC1_HW_TXQ1_QID 0x19
++#define TOE_GMAC1_HW_TXQ2_QID 0x1A
++#define TOE_GMAC1_HW_TXQ3_QID 0x1B
++#define TOE_GMAC0_DEFAULT_QID 0x20
++#define TOE_GMAC1_DEFAULT_QID 0x21
++#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
++#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
++
++/* TOE DMA Queue Size should be 2^n, n = 6...12
++ * TOE DMA Queues are the following queue types:
++ * SW Free Queue, HW Free Queue,
++ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
++ * The base address and descriptor number are configured at
++ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
++ */
++#define GET_WPTR(addr) readw((addr) + 2)
++#define GET_RPTR(addr) readw((addr))
++#define SET_WPTR(addr, data) writew((data), (addr) + 2)
++#define SET_RPTR(addr, data) writew((data), (addr))
++#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
++#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
++#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
++#define __RWPTR_MASK(order) ((1 << (order)) - 1)
++#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
++#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
++#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
++ __RWPTR_MASK((order)))
++
++/* Global registers */
++#define GLOBAL_TOE_VERSION_REG 0x0000
++#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
++#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
++#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
++#define GLOBAL_SWFQ_RWPTR_REG 0x0014
++#define GLOBAL_HWFQ_RWPTR_REG 0x0018
++#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
++#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
++#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
++#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
++#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
++#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
++#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
++#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
++#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
++#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
++#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
++#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
++#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
++#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
++#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
++#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
++#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
++
++/* GMAC 0/1 DMA/TOE register */
++#define GMAC_DMA_CTRL_REG 0x0000
++#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
++#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
++#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
++#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
++#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
++#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
++#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
++#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
++#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
++#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
++#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
++#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
++#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
++#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
++#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
++#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
++#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
++#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
++#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
++#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
++#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
++#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
++#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
++#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
++#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
++#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
++#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
++#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
++#define GMAC_HASH_ENGINE_REG0 0x0070
++#define GMAC_HASH_ENGINE_REG1 0x0074
++/* matching rule 0 Control register 0 */
++#define GMAC_MR0CR0 0x0078
++#define GMAC_MR0CR1 0x007C
++#define GMAC_MR0CR2 0x0080
++#define GMAC_MR1CR0 0x0084
++#define GMAC_MR1CR1 0x0088
++#define GMAC_MR1CR2 0x008C
++#define GMAC_MR2CR0 0x0090
++#define GMAC_MR2CR1 0x0094
++#define GMAC_MR2CR2 0x0098
++#define GMAC_MR3CR0 0x009C
++#define GMAC_MR3CR1 0x00A0
++#define GMAC_MR3CR2 0x00A4
++/* Support Protocol Register 0 */
++#define GMAC_SPR0 0x00A8
++#define GMAC_SPR1 0x00AC
++#define GMAC_SPR2 0x00B0
++#define GMAC_SPR3 0x00B4
++#define GMAC_SPR4 0x00B8
++#define GMAC_SPR5 0x00BC
++#define GMAC_SPR6 0x00C0
++#define GMAC_SPR7 0x00C4
++/* GMAC Hash/Rx/Tx AHB Weighting register */
++#define GMAC_AHB_WEIGHT_REG 0x00C8
++
++/* TOE GMAC 0/1 register */
++#define GMAC_STA_ADD0 0x0000
++#define GMAC_STA_ADD1 0x0004
++#define GMAC_STA_ADD2 0x0008
++#define GMAC_RX_FLTR 0x000c
++#define GMAC_MCAST_FIL0 0x0010
++#define GMAC_MCAST_FIL1 0x0014
++#define GMAC_CONFIG0 0x0018
++#define GMAC_CONFIG1 0x001c
++#define GMAC_CONFIG2 0x0020
++#define GMAC_CONFIG3 0x0024
++#define GMAC_RESERVED 0x0028
++#define GMAC_STATUS 0x002c
++#define GMAC_IN_DISCARDS 0x0030
++#define GMAC_IN_ERRORS 0x0034
++#define GMAC_IN_MCAST 0x0038
++#define GMAC_IN_BCAST 0x003c
++#define GMAC_IN_MAC1 0x0040 /* for STA 1 MAC Address */
++#define GMAC_IN_MAC2 0x0044 /* for STA 2 MAC Address */
++
++#define RX_STATS_NUM 6
++
++/* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
++union dma_q_base_size {
++ unsigned int bits32;
++ unsigned int base_size;
++};
++
++#define DMA_Q_BASE_MASK (~0x0f)
++
++/* DMA SKB Buffer register (offset 0x0008) */
++union dma_skb_size {
++ unsigned int bits32;
++ struct bit_0008 {
++ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
++ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
++ } bits;
++};
++
++/* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
++union dma_rwptr {
++ unsigned int bits32;
++ struct bit_000c {
++ unsigned int rptr : 16; /* Read Ptr, RO */
++ unsigned int wptr : 16; /* Write Ptr, RW */
++ } bits;
++};
++
++/* Interrupt Status Register 0 (offset 0x0020)
++ * Interrupt Mask Register 0 (offset 0x0024)
++ * Interrupt Select Register 0 (offset 0x0028)
++ */
++#define GMAC1_TXDERR_INT_BIT BIT(31)
++#define GMAC1_TXPERR_INT_BIT BIT(30)
++#define GMAC0_TXDERR_INT_BIT BIT(29)
++#define GMAC0_TXPERR_INT_BIT BIT(28)
++#define GMAC1_RXDERR_INT_BIT BIT(27)
++#define GMAC1_RXPERR_INT_BIT BIT(26)
++#define GMAC0_RXDERR_INT_BIT BIT(25)
++#define GMAC0_RXPERR_INT_BIT BIT(24)
++#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
++#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
++#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
++#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
++#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
++#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
++#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
++#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
++#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
++#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
++#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
++#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
++#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
++#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
++#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
++#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
++#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
++#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
++#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
++#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
++#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
++#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
++#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
++#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
++
++/* Interrupt Status Register 1 (offset 0x0030)
++ * Interrupt Mask Register 1 (offset 0x0034)
++ * Interrupt Select Register 1 (offset 0x0038)
++ */
++#define TOE_IQ3_FULL_INT_BIT BIT(31)
++#define TOE_IQ2_FULL_INT_BIT BIT(30)
++#define TOE_IQ1_FULL_INT_BIT BIT(29)
++#define TOE_IQ0_FULL_INT_BIT BIT(28)
++#define TOE_IQ3_INT_BIT BIT(27)
++#define TOE_IQ2_INT_BIT BIT(26)
++#define TOE_IQ1_INT_BIT BIT(25)
++#define TOE_IQ0_INT_BIT BIT(24)
++#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
++#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
++#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
++#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
++#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
++#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
++#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
++#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
++#define CLASS_RX_INT_BIT(x) BIT((x + 2))
++#define DEFAULT_Q1_INT_BIT BIT(1)
++#define DEFAULT_Q0_INT_BIT BIT(0)
++
++#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
++ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
++#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
++ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
++#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
++#define TOE_CLASS_RX_INT_BITS 0xfffc
++
++/* Interrupt Status Register 2 (offset 0x0040)
++ * Interrupt Mask Register 2 (offset 0x0044)
++ * Interrupt Select Register 2 (offset 0x0048)
++ */
++#define TOE_QL_FULL_INT_BIT(x) BIT(x)
++
++/* Interrupt Status Register 3 (offset 0x0050)
++ * Interrupt Mask Register 3 (offset 0x0054)
++ * Interrupt Select Register 3 (offset 0x0058)
++ */
++#define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
++
++/* Interrupt Status Register 4 (offset 0x0060)
++ * Interrupt Mask Register 4 (offset 0x0064)
++ * Interrupt Select Register 4 (offset 0x0068)
++ */
++#define GMAC1_RESERVED_INT_BIT BIT(31)
++#define GMAC1_MIB_INT_BIT BIT(30)
++#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
++#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
++#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
++#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
++#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
++#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
++#define GMAC0_RESERVED_INT_BIT BIT(23)
++#define GMAC0_MIB_INT_BIT BIT(22)
++#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
++#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
++#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
++#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
++#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
++#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
++#define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2)
++#define HWFQ_EMPTY_INT_BIT BIT(1)
++#define SWFQ_EMPTY_INT_BIT BIT(0)
++
++#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
++ GMAC0_RX_PAUSE_ON_INT_BIT | \
++ GMAC0_TX_PAUSE_ON_INT_BIT | \
++ GMAC0_RX_PAUSE_OFF_INT_BIT | \
++ GMAC0_TX_PAUSE_OFF_INT_BIT | \
++ GMAC0_RX_OVERRUN_INT_BIT | \
++ GMAC0_STATUS_CHANGE_INT_BIT)
++#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
++ GMAC1_RX_PAUSE_ON_INT_BIT | \
++ GMAC1_TX_PAUSE_ON_INT_BIT | \
++ GMAC1_RX_PAUSE_OFF_INT_BIT | \
++ GMAC1_TX_PAUSE_OFF_INT_BIT | \
++ GMAC1_RX_OVERRUN_INT_BIT | \
++ GMAC1_STATUS_CHANGE_INT_BIT)
++
++#define CLASS_RX_FULL_INT_BITS 0xfffc
++
++/* GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) */
++union queue_threshold {
++ unsigned int bits32;
++ struct bit_0070_2 {
++ /* 7:0 Software Free Queue Empty Threshold */
++ unsigned int swfq_empty:8;
++ /* 15:8 Hardware Free Queue Empty Threshold */
++ unsigned int hwfq_empty:8;
++ /* 23:16 */
++ unsigned int intrq:8;
++ /* 31:24 */
++ unsigned int toe_class:8;
++ } bits;
++};
++
++/* GMAC DMA Control Register
++ * GMAC0 offset 0x8000
++ * GMAC1 offset 0xC000
++ */
++union gmac_dma_ctrl {
++ unsigned int bits32;
++ struct bit_8000 {
++ /* bit 1:0 Peripheral Bus Width */
++ unsigned int td_bus:2;
++ /* bit 3:2 TxDMA max burst size for every AHB request */
++ unsigned int td_burst_size:2;
++ /* bit 7:4 TxDMA protection control */
++ unsigned int td_prot:4;
++ /* bit 9:8 Peripheral Bus Width */
++ unsigned int rd_bus:2;
++ /* bit 11:10 DMA max burst size for every AHB request */
++ unsigned int rd_burst_size:2;
++ /* bit 15:12 DMA Protection Control */
++ unsigned int rd_prot:4;
++ /* bit 17:16 */
++ unsigned int rd_insert_bytes:2;
++ /* bit 27:18 */
++ unsigned int reserved:10;
++ /* bit 28 1: Drop, 0: Accept */
++ unsigned int drop_small_ack:1;
++ /* bit 29 Loopback TxDMA to RxDMA */
++ unsigned int loopback:1;
++ /* bit 30 Tx DMA Enable */
++ unsigned int td_enable:1;
++ /* bit 31 Rx DMA Enable */
++ unsigned int rd_enable:1;
++ } bits;
++};
++
++/* GMAC Tx Weighting Control Register 0
++ * GMAC0 offset 0x8004
++ * GMAC1 offset 0xC004
++ */
++union gmac_tx_wcr0 {
++ unsigned int bits32;
++ struct bit_8004 {
++ /* bit 5:0 HW TX Queue 3 */
++ unsigned int hw_tq0:6;
++ /* bit 11:6 HW TX Queue 2 */
++ unsigned int hw_tq1:6;
++ /* bit 17:12 HW TX Queue 1 */
++ unsigned int hw_tq2:6;
++ /* bit 23:18 HW TX Queue 0 */
++ unsigned int hw_tq3:6;
++ /* bit 31:24 */
++ unsigned int reserved:8;
++ } bits;
++};
++
++/* GMAC Tx Weighting Control Register 1
++ * GMAC0 offset 0x8008
++ * GMAC1 offset 0xC008
++ */
++union gmac_tx_wcr1 {
++ unsigned int bits32;
++ struct bit_8008 {
++ /* bit 4:0 SW TX Queue 0 */
++ unsigned int sw_tq0:5;
++ /* bit 9:5 SW TX Queue 1 */
++ unsigned int sw_tq1:5;
++ /* bit 14:10 SW TX Queue 2 */
++ unsigned int sw_tq2:5;
++ /* bit 19:15 SW TX Queue 3 */
++ unsigned int sw_tq3:5;
++ /* bit 24:20 SW TX Queue 4 */
++ unsigned int sw_tq4:5;
++ /* bit 29:25 SW TX Queue 5 */
++ unsigned int sw_tq5:5;
++ /* bit 31:30 */
++ unsigned int reserved:2;
++ } bits;
++};
++
++/* GMAC DMA Tx Description Word 0 Register
++ * GMAC0 offset 0x8040
++ * GMAC1 offset 0xC040
++ */
++union gmac_txdesc_0 {
++ unsigned int bits32;
++ struct bit_8040 {
++ /* bit 15:0 Transfer size */
++ unsigned int buffer_size:16;
++ /* bit 21:16 number of descriptors used for the current frame */
++ unsigned int desc_count:6;
++ /* bit 22 Tx Status, 1: Successful 0: Failed */
++ unsigned int status_tx_ok:1;
++ /* bit 28:23 Tx Status, Reserved bits */
++ unsigned int status_rvd:6;
++ /* bit 29 protocol error during processing this descriptor */
++ unsigned int perr:1;
++ /* bit 30 data error during processing this descriptor */
++ unsigned int derr:1;
++ /* bit 31 */
++ unsigned int reserved:1;
++ } bits;
++};
++
++/* GMAC DMA Tx Description Word 1 Register
++ * GMAC0 offset 0x8044
++ * GMAC1 offset 0xC044
++ */
++union gmac_txdesc_1 {
++ unsigned int bits32;
++ struct txdesc_word1 {
++ /* bit 15: 0 Tx Frame Byte Count */
++ unsigned int byte_count:16;
++ /* bit 16 TSS segmentation use MTU setting */
++ unsigned int mtu_enable:1;
++ /* bit 17 IPV4 Header Checksum Enable */
++ unsigned int ip_chksum:1;
++ /* bit 18 IPV6 Tx Enable */
++ unsigned int ipv6_enable:1;
++ /* bit 19 TCP Checksum Enable */
++ unsigned int tcp_chksum:1;
++ /* bit 20 UDP Checksum Enable */
++ unsigned int udp_chksum:1;
++ /* bit 21 Bypass HW offload engine */
++ unsigned int bypass_tss:1;
++ /* bit 22 Don't update IP length field */
++ unsigned int ip_fixed_len:1;
++ /* bit 31:23 Tx Flag, Reserved */
++ unsigned int reserved:9;
++ } bits;
++};
++
++#define TSS_IP_FIXED_LEN_BIT BIT(22)
++#define TSS_BYPASS_BIT BIT(21)
++#define TSS_UDP_CHKSUM_BIT BIT(20)
++#define TSS_TCP_CHKSUM_BIT BIT(19)
++#define TSS_IPV6_ENABLE_BIT BIT(18)
++#define TSS_IP_CHKSUM_BIT BIT(17)
++#define TSS_MTU_ENABLE_BIT BIT(16)
++
++#define TSS_CHECKUM_ENABLE \
++ (TSS_IP_CHKSUM_BIT | TSS_IPV6_ENABLE_BIT | \
++ TSS_TCP_CHKSUM_BIT | TSS_UDP_CHKSUM_BIT)
++
++/* GMAC DMA Tx Description Word 2 Register
++ * GMAC0 offset 0x8048
++ * GMAC1 offset 0xC048
++ */
++union gmac_txdesc_2 {
++ unsigned int bits32;
++ unsigned int buf_adr;
++};
++
++/* GMAC DMA Tx Description Word 3 Register
++ * GMAC0 offset 0x804C
++ * GMAC1 offset 0xC04C
++ */
++union gmac_txdesc_3 {
++ unsigned int bits32;
++ struct txdesc_word3 {
++ /* bit 12: 0 Tx Frame Byte Count */
++ unsigned int mtu_size:13;
++ /* bit 28:13 */
++ unsigned int reserved:16;
++ /* bit 29 End of frame interrupt enable */
++ unsigned int eofie:1;
++ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
++ unsigned int sof_eof:2;
++ } bits;
++};
++
++#define SOF_EOF_BIT_MASK 0x3fffffff
++#define SOF_BIT 0x80000000
++#define EOF_BIT 0x40000000
++#define EOFIE_BIT BIT(29)
++#define MTU_SIZE_BIT_MASK 0x1fff
++
++/* GMAC Tx Descriptor */
++struct gmac_txdesc {
++ union gmac_txdesc_0 word0;
++ union gmac_txdesc_1 word1;
++ union gmac_txdesc_2 word2;
++ union gmac_txdesc_3 word3;
++};
++
++/* GMAC DMA Rx Description Word 0 Register
++ * GMAC0 offset 0x8060
++ * GMAC1 offset 0xC060
++ */
++union gmac_rxdesc_0 {
++ unsigned int bits32;
++ struct bit_8060 {
++ /* bit 15:0 number of descriptors used for the current frame */
++ unsigned int buffer_size:16;
++ /* bit 21:16 number of descriptors used for the current frame */
++ unsigned int desc_count:6;
++ /* bit 24:22 Status of rx frame */
++ unsigned int status:4;
++ /* bit 28:26 Check Sum Status */
++ unsigned int chksum_status:3;
++ /* bit 29 protocol error during processing this descriptor */
++ unsigned int perr:1;
++ /* bit 30 data error during processing this descriptor */
++ unsigned int derr:1;
++ /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
++ unsigned int drop:1;
++ } bits;
++};
++
++#define GMAC_RXDESC_0_T_derr BIT(30)
++#define GMAC_RXDESC_0_T_perr BIT(29)
++#define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26)
++#define GMAC_RXDESC_0_T_status(x) BIT(x + 22)
++#define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16)
++
++#define RX_CHKSUM_IP_UDP_TCP_OK 0
++#define RX_CHKSUM_IP_OK_ONLY 1
++#define RX_CHKSUM_NONE 2
++#define RX_CHKSUM_IP_ERR_UNKNOWN 4
++#define RX_CHKSUM_IP_ERR 5
++#define RX_CHKSUM_TCP_UDP_ERR 6
++#define RX_CHKSUM_NUM 8
++
++#define RX_STATUS_GOOD_FRAME 0
++#define RX_STATUS_TOO_LONG_GOOD_CRC 1
++#define RX_STATUS_RUNT_FRAME 2
++#define RX_STATUS_SFD_NOT_FOUND 3
++#define RX_STATUS_CRC_ERROR 4
++#define RX_STATUS_TOO_LONG_BAD_CRC 5
++#define RX_STATUS_ALIGNMENT_ERROR 6
++#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
++#define RX_STATUS_RX_ERR 8
++#define RX_STATUS_DA_FILTERED 9
++#define RX_STATUS_BUFFER_FULL 10
++#define RX_STATUS_NUM 16
++
++#define RX_ERROR_LENGTH(s) \
++ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
++ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
++#define RX_ERROR_OVER(s) \
++ ((s) == RX_STATUS_BUFFER_FULL)
++#define RX_ERROR_CRC(s) \
++ ((s) == RX_STATUS_CRC_ERROR || \
++ (s) == RX_STATUS_TOO_LONG_BAD_CRC)
++#define RX_ERROR_FRAME(s) \
++ ((s) == RX_STATUS_ALIGNMENT_ERROR || \
++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
++#define RX_ERROR_FIFO(s) \
++ (0)
++
++/* GMAC DMA Rx Description Word 1 Register
++ * GMAC0 offset 0x8064
++ * GMAC1 offset 0xC064
++ */
++union gmac_rxdesc_1 {
++ unsigned int bits32;
++ struct rxdesc_word1 {
++ /* bit 15: 0 Rx Frame Byte Count */
++ unsigned int byte_count:16;
++ /* bit 31:16 Software ID */
++ unsigned int sw_id:16;
++ } bits;
++};
++
++/* GMAC DMA Rx Description Word 2 Register
++ * GMAC0 offset 0x8068
++ * GMAC1 offset 0xC068
++ */
++union gmac_rxdesc_2 {
++ unsigned int bits32;
++ unsigned int buf_adr;
++};
++
++#define RX_INSERT_NONE 0
++#define RX_INSERT_1_BYTE 1
++#define RX_INSERT_2_BYTE 2
++#define RX_INSERT_3_BYTE 3
++
++/* GMAC DMA Rx Description Word 3 Register
++ * GMAC0 offset 0x806C
++ * GMAC1 offset 0xC06C
++ */
++union gmac_rxdesc_3 {
++ unsigned int bits32;
++ struct rxdesc_word3 {
++ /* bit 7: 0 L3 data offset */
++ unsigned int l3_offset:8;
++ /* bit 15: 8 L4 data offset */
++ unsigned int l4_offset:8;
++ /* bit 23: 16 L7 data offset */
++ unsigned int l7_offset:8;
++ /* bit 24 Duplicated ACK detected */
++ unsigned int dup_ack:1;
++ /* bit 25 abnormal case found */
++ unsigned int abnormal:1;
++ /* bit 26 IPV4 option or IPV6 extension header */
++ unsigned int option:1;
++ /* bit 27 Out of Sequence packet */
++ unsigned int out_of_seq:1;
++ /* bit 28 Control Flag is present */
++ unsigned int ctrl_flag:1;
++ /* bit 29 End of frame interrupt enable */
++ unsigned int eofie:1;
++ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
++ unsigned int sof_eof:2;
++ } bits;
++};
++
++/* GMAC Rx Descriptor, this is simply fitted over the queue registers */
++struct gmac_rxdesc {
++ union gmac_rxdesc_0 word0;
++ union gmac_rxdesc_1 word1;
++ union gmac_rxdesc_2 word2;
++ union gmac_rxdesc_3 word3;
++};
++
++/* GMAC Matching Rule Control Register 0
++ * GMAC0 offset 0x8078
++ * GMAC1 offset 0xC078
++ */
++#define MR_L2_BIT BIT(31)
++#define MR_L3_BIT BIT(30)
++#define MR_L4_BIT BIT(29)
++#define MR_L7_BIT BIT(28)
++#define MR_PORT_BIT BIT(27)
++#define MR_PRIORITY_BIT BIT(26)
++#define MR_DA_BIT BIT(23)
++#define MR_SA_BIT BIT(22)
++#define MR_ETHER_TYPE_BIT BIT(21)
++#define MR_VLAN_BIT BIT(20)
++#define MR_PPPOE_BIT BIT(19)
++#define MR_IP_VER_BIT BIT(15)
++#define MR_IP_HDR_LEN_BIT BIT(14)
++#define MR_FLOW_LABLE_BIT BIT(13)
++#define MR_TOS_TRAFFIC_BIT BIT(12)
++#define MR_SPR_BIT(x) BIT(x)
++#define MR_SPR_BITS 0xff
++
++/* GMAC_AHB_WEIGHT registers
++ * GMAC0 offset 0x80C8
++ * GMAC1 offset 0xC0C8
++ */
++union gmac_ahb_weight {
++ unsigned int bits32;
++ struct bit_80C8 {
++ /* 4:0 */
++ unsigned int hash_weight:5;
++ /* 9:5 */
++ unsigned int rx_weight:5;
++ /* 14:10 */
++ unsigned int tx_weight:5;
++ /* 19:15 Rx Data Pre Request FIFO Threshold */
++ unsigned int pre_req:5;
++ /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
++ unsigned int tq_dv_threshold:5;
++ /* 31:25 */
++ unsigned int reserved:7;
++ } bits;
++};
++
++/* GMAC RX FLTR
++ * GMAC0 Offset 0xA00C
++ * GMAC1 Offset 0xE00C
++ */
++union gmac_rx_fltr {
++ unsigned int bits32;
++ struct bit1_000c {
++ /* Enable receive of unicast frames that are sent to STA
++ * address
++ */
++ unsigned int unicast:1;
++ /* Enable receive of multicast frames that pass multicast
++ * filter
++ */
++ unsigned int multicast:1;
++ /* Enable receive of broadcast frames */
++ unsigned int broadcast:1;
++ /* Enable receive of all frames */
++ unsigned int promiscuous:1;
++ /* Enable receive of all error frames */
++ unsigned int error:1;
++ unsigned int reserved:27;
++ } bits;
++};
++
++/* GMAC Configuration 0
++ * GMAC0 Offset 0xA018
++ * GMAC1 Offset 0xE018
++ */
++union gmac_config0 {
++ unsigned int bits32;
++ struct bit1_0018 {
++ /* 0: disable transmit */
++ unsigned int dis_tx:1;
++ /* 1: disable receive */
++ unsigned int dis_rx:1;
++ /* 2: transmit data loopback enable */
++ unsigned int loop_back:1;
++ /* 3: flow control also trigged by Rx queues */
++ unsigned int flow_ctrl:1;
++ /* 4-7: adjust IFG from 96+/-56 */
++ unsigned int adj_ifg:4;
++ /* 8-10 maximum receive frame length allowed */
++ unsigned int max_len:3;
++ /* 11: disable back-off function */
++ unsigned int dis_bkoff:1;
++ /* 12: disable 16 collisions abort function */
++ unsigned int dis_col:1;
++ /* 13: speed up timers in simulation */
++ unsigned int sim_test:1;
++ /* 14: RX flow control enable */
++ unsigned int rx_fc_en:1;
++ /* 15: TX flow control enable */
++ unsigned int tx_fc_en:1;
++ /* 16: RGMII in-band status enable */
++ unsigned int rgmii_en:1;
++ /* 17: IPv4 RX Checksum enable */
++ unsigned int ipv4_rx_chksum:1;
++ /* 18: IPv6 RX Checksum enable */
++ unsigned int ipv6_rx_chksum:1;
++ /* 19: Remove Rx VLAN tag */
++ unsigned int rx_tag_remove:1;
++ /* 20 */
++ unsigned int rgmm_edge:1;
++ /* 21 */
++ unsigned int rxc_inv:1;
++ /* 22 */
++ unsigned int ipv6_exthdr_order:1;
++ /* 23 */
++ unsigned int rx_err_detect:1;
++ /* 24 */
++ unsigned int port0_chk_hwq:1;
++ /* 25 */
++ unsigned int port1_chk_hwq:1;
++ /* 26 */
++ unsigned int port0_chk_toeq:1;
++ /* 27 */
++ unsigned int port1_chk_toeq:1;
++ /* 28 */
++ unsigned int port0_chk_classq:1;
++ /* 29 */
++ unsigned int port1_chk_classq:1;
++ /* 30, 31 */
++ unsigned int reserved:2;
++ } bits;
++};
++
++#define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0))
++#define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17))
++#define CONFIG0_FLOW_RX BIT(14)
++#define CONFIG0_FLOW_TX BIT(15)
++#define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15))
++#define CONFIG0_FLOW_CTL (BIT(14) | BIT(15))
++
++#define CONFIG0_MAXLEN_SHIFT 8
++#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
++#define CONFIG0_MAXLEN_1536 0
++#define CONFIG0_MAXLEN_1518 1
++#define CONFIG0_MAXLEN_1522 2
++#define CONFIG0_MAXLEN_1542 3
++#define CONFIG0_MAXLEN_9k 4 /* 9212 */
++#define CONFIG0_MAXLEN_10k 5 /* 10236 */
++#define CONFIG0_MAXLEN_1518__6 6
++#define CONFIG0_MAXLEN_1518__7 7
++
++/* GMAC Configuration 1
++ * GMAC0 Offset 0xA01C
++ * GMAC1 Offset 0xE01C
++ */
++union gmac_config1 {
++ unsigned int bits32;
++ struct bit1_001c {
++ /* Flow control set threshold */
++ unsigned int set_threshold:8;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:8;
++ unsigned int reserved:16;
++ } bits;
++};
++
++#define GMAC_FLOWCTRL_SET_MAX 32
++#define GMAC_FLOWCTRL_SET_MIN 0
++#define GMAC_FLOWCTRL_RELEASE_MAX 32
++#define GMAC_FLOWCTRL_RELEASE_MIN 0
++
++/* GMAC Configuration 2
++ * GMAC0 Offset 0xA020
++ * GMAC1 Offset 0xE020
++ */
++union gmac_config2 {
++ unsigned int bits32;
++ struct bit1_0020 {
++ /* Flow control set threshold */
++ unsigned int set_threshold:16;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:16;
++ } bits;
++};
++
++/* GMAC Configuration 3
++ * GMAC0 Offset 0xA024
++ * GMAC1 Offset 0xE024
++ */
++union gmac_config3 {
++ unsigned int bits32;
++ struct bit1_0024 {
++ /* Flow control set threshold */
++ unsigned int set_threshold:16;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:16;
++ } bits;
++};
++
++/* GMAC STATUS
++ * GMAC0 Offset 0xA02C
++ * GMAC1 Offset 0xE02C
++ */
++union gmac_status {
++ unsigned int bits32;
++ struct bit1_002c {
++ /* Link status */
++ unsigned int link:1;
++ /* Link speed(00->2.5M 01->25M 10->125M) */
++ unsigned int speed:2;
++ /* Duplex mode */
++ unsigned int duplex:1;
++ unsigned int reserved_1:1;
++ /* PHY interface type */
++ unsigned int mii_rmii:2;
++ unsigned int reserved_2:25;
++ } bits;
++};
++
++#define GMAC_SPEED_10 0
++#define GMAC_SPEED_100 1
++#define GMAC_SPEED_1000 2
++
++#define GMAC_PHY_MII 0
++#define GMAC_PHY_GMII 1
++#define GMAC_PHY_RGMII_100_10 2
++#define GMAC_PHY_RGMII_1000 3
++
++/* Queue Header
++ * (1) TOE Queue Header
++ * (2) Non-TOE Queue Header
++ * (3) Interrupt Queue Header
++ *
++ * memory Layout
++ * TOE Queue Header
++ * 0x60003000 +---------------------------+ 0x0000
++ * | TOE Queue 0 Header |
++ * | 8 * 4 Bytes |
++ * +---------------------------+ 0x0020
++ * | TOE Queue 1 Header |
++ * | 8 * 4 Bytes |
++ * +---------------------------+ 0x0040
++ * | ...... |
++ * | |
++ * +---------------------------+
++ *
++ * Non TOE Queue Header
++ * 0x60002000 +---------------------------+ 0x0000
++ * | Default Queue 0 Header |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x0008
++ * | Default Queue 1 Header |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x0010
++ * | Classification Queue 0 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Classification Queue 1 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ (n * 8 + 0x10)
++ * | ... |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ (13 * 8 + 0x10)
++ * | Classification Queue 13 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x80
++ * | Interrupt Queue 0 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 1 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 2 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 3 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ *
++ */
++#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
++#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
++#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
++#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
++#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
++#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
++#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
++
++/* NONTOE Queue Header Word 0 */
++union nontoe_qhdr0 {
++ unsigned int bits32;
++ unsigned int base_size;
++};
++
++#define NONTOE_QHDR0_BASE_MASK (~0x0f)
++
++/* NONTOE Queue Header Word 1 */
++union nontoe_qhdr1 {
++ unsigned int bits32;
++ struct bit_nonqhdr1 {
++ /* bit 15:0 */
++ unsigned int rptr:16;
++ /* bit 31:16 */
++ unsigned int wptr:16;
++ } bits;
++};
++
++/* Non-TOE Queue Header */
++struct nontoe_qhdr {
++ union nontoe_qhdr0 word0;
++ union nontoe_qhdr1 word1;
++};
++
++#endif /* _GEMINI_ETHERNET_H */
--- /dev/null
+From 860005c1a2f16aaa33458a7d80c9728b710ae292 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 6 Nov 2017 00:05:28 +0100
+Subject: [PATCH 23/31] ARM: dts: Add ethernet to the Gemini SoC
+
+This adds the Gemini ethernet node to the Gemini SoC.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 43 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -114,9 +114,16 @@
+ };
+ };
+ gmii_default_pins: pinctrl-gmii {
++ /*
++ * Only activate GMAC0 by default since
++ * GMAC1 will overlap with 8 GPIO lines
++ * gpio2a, gpio2b. Overlay groups with
++ * "gmii_gmac0_grp", "gmii_gmac1_grp" for
++ * both ethernet interfaces.
++ */
+ mux {
+ function = "gmii";
+- groups = "gmiigrp";
++ groups = "gmii_gmac0_grp";
+ };
+ };
+ pci_default_pins: pinctrl-pci {
+@@ -316,6 +323,41 @@
+ };
+ };
+
++ ethernet@60000000 {
++ compatible = "cortina,gemini-ethernet";
++ reg = <0x60000000 0x4000>, /* Global registers, queue */
++ <0x60004000 0x2000>, /* V-bit */
++ <0x60006000 0x2000>; /* A-bit */
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmii_default_pins>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ gmac0: ethernet-port@0 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
++ <0x6000a000 0x2000>; /* Port 0 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC0>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
++ clock-names = "PCLK";
++ };
++
++ gmac1: ethernet-port@1 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
++ <0x6000e000 0x2000>; /* Port 1 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC1>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
++ clock-names = "PCLK";
++ };
++ };
++
+ ata@63000000 {
+ compatible = "cortina,gemini-pata", "faraday,ftide010";
+ reg = <0x63000000 0x1000>;
--- /dev/null
+From e0a7c7762e3a81e908bcca4176139ea9755d0985 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 21 Jan 2018 14:15:41 +0100
+Subject: [PATCH 24/31] net: gemini: Depend on HAS_IOMEM
+
+The zeroday builder notices that since Usermode Linux does not
+have IO memory, the build fails for them when selecting everything
+it can enable.
+
+As the driver is clearly using memory-mapped registers to access
+the network adapter, we add depends on HAS_IOMEM to solve this
+problem.
+
+Reported-by: kbuild test robot <fengguang.wu@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/cortina/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/cortina/Kconfig
++++ b/drivers/net/ethernet/cortina/Kconfig
+@@ -14,6 +14,7 @@ if NET_VENDOR_CORTINA
+ config GEMINI_ETHERNET
+ tristate "Gemini Gigabit Ethernet support"
+ depends on OF
++ depends on HAS_IOMEM
+ select PHYLIB
+ select CRC32
+ ---help---
--- /dev/null
+From f30cc6acdeb834be1a6ae54d47c84b2f8012b83d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 18 Jan 2018 14:36:21 +0100
+Subject: [PATCH 25/31] ARM: dts: Set D-Link DNS-313 SATA to muxmode 0
+
+This stops the driver from trying to probe the ATA slave
+interface. The vendor code enables the slave interface
+but the driver in the vendor tree does not make use of
+it.
+
+Setting it to muxmode 0 disables the slave interface:
+the hardware only has the master interface connected
+to the one harddrive slot anyways.
+
+Without this change booting takes excessive time, so it
+is very annoying to end users.
+
+Fixes: dd5c0561db75 ("ARM: dts: Add basic devicetree for D-Link DNS-313")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ARM SoC folks: please apply this for fixes for v4.16.
+---
+ arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+@@ -219,7 +219,7 @@
+
+ sata: sata@46000000 {
+ /* The ROM uses this muxmode */
+- cortina,gemini-ata-muxmode = <3>;
++ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+ };
--- /dev/null
+From da443bc125265cae24a0e5f7d1c7bba196a9319f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 22 Feb 2018 08:34:35 +0100
+Subject: [PATCH 26/31] power: gemini-poweroff: Avoid spurious poweroff
+
+On the D-Link DIR-685 we get spurious poweroff from
+infrared. Since that block (CIR) doesn't even have a
+driver this can be safely ignored, we can revisit this
+code once we have a device supporting CIR.
+
+On the D-Link DNS-313 we get spurious poweroff from
+the power button. This appears to be an initialization
+issue: we need to enable the block (start the state
+machine) before we clear any dangling IRQ.
+
+This patch fixes both issues.
+
+Fixes: f7a388d6cd1c ("power: reset: Add a driver for the Gemini poweroff")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ChangeLog v1->v2:
+- Fix both issues and rename the patch.
+- Proper commit message with specifics.
+---
+ drivers/power/reset/gemini-poweroff.c | 30 +++++++++++++++++-------------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+--- a/drivers/power/reset/gemini-poweroff.c
++++ b/drivers/power/reset/gemini-poweroff.c
+@@ -47,8 +47,12 @@ static irqreturn_t gemini_powerbutton_in
+ val &= 0x70U;
+ switch (val) {
+ case GEMINI_STAT_CIR:
+- dev_info(gpw->dev, "infrared poweroff\n");
+- orderly_poweroff(true);
++ /*
++ * We do not yet have a driver for the infrared
++ * controller so it can cause spurious poweroff
++ * events. Ignore those for now.
++ */
++ dev_info(gpw->dev, "infrared poweroff - ignored\n");
+ break;
+ case GEMINI_STAT_RTC:
+ dev_info(gpw->dev, "RTC poweroff\n");
+@@ -116,7 +120,17 @@ static int gemini_poweroff_probe(struct
+ return -ENODEV;
+ }
+
+- /* Clear the power management IRQ */
++ /*
++ * Enable the power controller. This is crucial on Gemini
++ * systems: if this is not done, pressing the power button
++ * will result in unconditional poweroff without any warning.
++ * This makes the kernel handle the poweroff.
++ */
++ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
++ val |= GEMINI_CTRL_ENABLE;
++ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
++
++ /* Now that the state machine is active, clear the IRQ */
+ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+ val |= GEMINI_CTRL_IRQ_CLR;
+ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+@@ -129,16 +143,6 @@ static int gemini_poweroff_probe(struct
+ pm_power_off = gemini_poweroff;
+ gpw_poweroff = gpw;
+
+- /*
+- * Enable the power controller. This is crucial on Gemini
+- * systems: if this is not done, pressing the power button
+- * will result in unconditional poweroff without any warning.
+- * This makes the kernel handle the poweroff.
+- */
+- val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+- val |= GEMINI_CTRL_ENABLE;
+- writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+-
+ dev_info(dev, "Gemini poweroff driver registered\n");
+
+ return 0;
--- /dev/null
+From 3699f119ff8da021fe7a1759e98e38ca88fa6766 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Date: Wed, 8 Feb 2017 21:00:09 +0100
+Subject: [PATCH 27/31] usb: host: add DT bindings for faraday fotg2
+
+This adds device tree bindings for the Faraday FOTG2
+dual-mode host controller.
+
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ChangeLog v1->v3:
+- Change compatible to "faraday,fotg210" as the name of the
+ hardware block.
+- Add an elaborate SoC-specific compatible string for the
+ Cortina Systems Gemini so that SoC-specific features can
+ be enabled.
+- Add cortina,gemini-mini-b to indicate a Gemini PHY with
+ a Mini-B adapter connected.
+- Indicated that the Gemini version can handle "wakeup-source".
+- Add optional IP block clock.
+---
+ .../devicetree/bindings/usb/faraday,fotg210.txt | 35 ++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/faraday,fotg210.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/faraday,fotg210.txt
+@@ -0,0 +1,35 @@
++Faraday FOTG Host controller
++
++This OTG-capable USB host controller is found in Cortina Systems
++Gemini and other SoC products.
++
++Required properties:
++- compatible: should be one of:
++ "faraday,fotg210"
++ "cortina,gemini-usb", "faraday,fotg210"
++- reg: should contain one register range i.e. start and length
++- interrupts: description of the interrupt line
++
++Optional properties:
++- clocks: should contain the IP block clock
++- clock-names: should be "PCLK" for the IP block clock
++
++Required properties for "cortina,gemini-usb" compatible:
++- syscon: a phandle to the system controller to access PHY registers
++
++Optional properties for "cortina,gemini-usb" compatible:
++- cortina,gemini-mini-b: boolean property that indicates that a Mini-B
++ OTH connector is in use
++- wakeup-source: see power/wakeup-source.txt
++
++Example for Gemini:
++
++usb@68000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x68000000 0x1000>;
++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cc 12>;
++ clock-names = "PCLK";
++ syscon = <&syscon>;
++ wakeup-source;
++};
--- /dev/null
+From 5662c553e89ac4179ec2a7a94a342ba3e5d78cf7 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Date: Thu, 9 Feb 2017 15:20:49 +0100
+Subject: [PATCH 28/31] usb: host: fotg2: add device tree probing
+
+Add device tree probing to the fotg2 driver.
+
+Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ChangeLog v2->v3:
+- Change compatible to "faraday,fotg210" simply.
+---
+ drivers/usb/host/fotg210-hcd.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -23,6 +23,7 @@
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+ #include <linux/module.h>
++#include <linux/of.h>
+ #include <linux/device.h>
+ #include <linux/dmapool.h>
+ #include <linux/kernel.h>
+@@ -5600,6 +5601,15 @@ static int fotg210_hcd_probe(struct plat
+ if (usb_disabled())
+ return -ENODEV;
+
++ /* Right now device-tree probed devices don't get dma_mask set.
++ * Since shared usb code relies on it, set it here for now.
++ * Once we have dma capability bindings this can go away.
++ */
++
++ retval = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
++ if (retval)
++ goto fail_create_hcd;
++
+ pdev->dev.power.power_state = PMSG_ON;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+@@ -5676,9 +5686,18 @@ static int fotg210_hcd_remove(struct pla
+ return 0;
+ }
+
++#ifdef CONFIG_OF
++static const struct of_device_id fotg210_of_match[] = {
++ { .compatible = "faraday,fotg210" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, fotg210_of_match);
++#endif
++
+ static struct platform_driver fotg210_hcd_driver = {
+ .driver = {
+ .name = "fotg210-hcd",
++ .of_match_table = of_match_ptr(fotg210_of_match),
+ },
+ .probe = fotg210_hcd_probe,
+ .remove = fotg210_hcd_remove,
--- /dev/null
+From acd19633751f14607ccd76f9dfde5bde7935766c Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 21 Apr 2017 20:46:12 +0200
+Subject: [PATCH 29/31] usb: host: fotg2: add silicon clock handling
+
+When used in a system with software-controller silicon clocks,
+the FOTG210 needs to grab, prepare and enable the clock.
+This is needed on for example the Cortina Gemini, where the
+platform will by default gate off the clock unless the
+peripheral (in this case the USB driver) grabs and enables
+the clock.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/usb/host/fotg210-hcd.c | 26 ++++++++++++++++++++++----
+ drivers/usb/host/fotg210.h | 3 +++
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -45,6 +45,7 @@
+ #include <linux/uaccess.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/clk.h>
+
+ #include <asm/byteorder.h>
+ #include <asm/irq.h>
+@@ -5635,7 +5636,7 @@ static int fotg210_hcd_probe(struct plat
+ hcd->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hcd->regs)) {
+ retval = PTR_ERR(hcd->regs);
+- goto failed;
++ goto failed_put_hcd;
+ }
+
+ hcd->rsrc_start = res->start;
+@@ -5645,22 +5646,35 @@ static int fotg210_hcd_probe(struct plat
+
+ fotg210->caps = hcd->regs;
+
++ /* It's OK not to supply this clock */
++ fotg210->pclk = clk_get(dev, "PCLK");
++ if (!IS_ERR(fotg210->pclk)) {
++ retval = clk_prepare_enable(fotg210->pclk);
++ if (retval) {
++ dev_err(dev, "failed to enable PCLK\n");
++ goto failed_dis_clk;
++ }
++ }
++
+ retval = fotg210_setup(hcd);
+ if (retval)
+- goto failed;
++ goto failed_dis_clk;
+
+ fotg210_init(fotg210);
+
+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
+ if (retval) {
+ dev_err(dev, "failed to add hcd with err %d\n", retval);
+- goto failed;
++ goto failed_dis_clk;
+ }
+ device_wakeup_enable(hcd->self.controller);
+
+ return retval;
+
+-failed:
++failed_dis_clk:
++ if (!IS_ERR(fotg210->pclk))
++ clk_disable_unprepare(fotg210->pclk);
++failed_put_hcd:
+ usb_put_hcd(hcd);
+ fail_create_hcd:
+ dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
+@@ -5676,6 +5690,10 @@ static int fotg210_hcd_remove(struct pla
+ {
+ struct device *dev = &pdev->dev;
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
++ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
++
++ if (!IS_ERR(fotg210->pclk))
++ clk_disable_unprepare(fotg210->pclk);
+
+ if (!hcd)
+ return 0;
+--- a/drivers/usb/host/fotg210.h
++++ b/drivers/usb/host/fotg210.h
+@@ -182,6 +182,9 @@ struct fotg210_hcd { /* one per contro
+ # define COUNT(x)
+ #endif
+
++ /* silicon clock */
++ struct clk *pclk;
++
+ /* debug files */
+ struct dentry *debug_dir;
+ };
--- /dev/null
+From e8ede0f62b39a3d3b06ae3dc04a74680a1f0a64b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 21 Apr 2017 22:19:00 +0200
+Subject: [PATCH 30/31] usb: host: fotg2: add Gemini-specific handling
+
+The Cortina Systems Gemini has bolted on a PHY inside the
+silicon that can be handled by six bits in a MISC register in
+the system controller.
+
+If we are running on Gemini, look up a syscon regmap through
+a phandle and enable VBUS and optionally the Mini-B connector.
+
+If the device is flagged as "wakeup-source" using the standard
+DT bindings, we also enable this in the global controller for
+respective port.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/usb/host/Kconfig | 1 +
+ drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 77 insertions(+)
+
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -375,6 +375,7 @@ config USB_ISP1362_HCD
+ config USB_FOTG210_HCD
+ tristate "FOTG210 HCD support"
+ depends on USB && HAS_DMA && HAS_IOMEM
++ select MFD_SYSCON
+ ---help---
+ Faraday FOTG210 is an OTG controller which can be configured as
+ an USB2.0 host. It is designed to meet USB2.0 EHCI specification
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -46,6 +46,10 @@
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ #include <linux/clk.h>
++#include <linux/bitops.h>
++/* For Cortina Gemini */
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
+
+ #include <asm/byteorder.h>
+ #include <asm/irq.h>
+@@ -5583,6 +5587,72 @@ static void fotg210_init(struct fotg210_
+ iowrite32(value, &fotg210->regs->otgcsr);
+ }
+
++/*
++ * Gemini-specific initialization function, only executed on the
++ * Gemini SoC using the global misc control register.
++ */
++#define GEMINI_GLOBAL_MISC_CTRL 0x30
++#define GEMINI_MISC_USB0_WAKEUP BIT(14)
++#define GEMINI_MISC_USB1_WAKEUP BIT(15)
++#define GEMINI_MISC_USB0_VBUS_ON BIT(22)
++#define GEMINI_MISC_USB1_VBUS_ON BIT(23)
++#define GEMINI_MISC_USB0_MINI_B BIT(29)
++#define GEMINI_MISC_USB1_MINI_B BIT(30)
++
++static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd)
++{
++ struct device_node *np = dev->of_node;
++ struct regmap *map;
++ bool mini_b;
++ bool wakeup;
++ u32 mask, val;
++ int ret;
++
++ map = syscon_regmap_lookup_by_phandle(np, "syscon");
++ if (IS_ERR(map)) {
++ dev_err(dev, "no syscon\n");
++ return PTR_ERR(map);
++ }
++ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b");
++ wakeup = of_property_read_bool(np, "wakeup-source");
++
++ /*
++ * Figure out if this is USB0 or USB1 by simply checking the
++ * physical base address.
++ */
++ mask = 0;
++ if (hcd->rsrc_start == 0x69000000) {
++ val = GEMINI_MISC_USB1_VBUS_ON;
++ if (mini_b)
++ val |= GEMINI_MISC_USB1_MINI_B;
++ else
++ mask |= GEMINI_MISC_USB1_MINI_B;
++ if (wakeup)
++ val |= GEMINI_MISC_USB1_WAKEUP;
++ else
++ mask |= GEMINI_MISC_USB1_WAKEUP;
++ } else {
++ val = GEMINI_MISC_USB0_VBUS_ON;
++ if (mini_b)
++ val |= GEMINI_MISC_USB0_MINI_B;
++ else
++ mask |= GEMINI_MISC_USB0_MINI_B;
++ if (wakeup)
++ val |= GEMINI_MISC_USB0_WAKEUP;
++ else
++ mask |= GEMINI_MISC_USB0_WAKEUP;
++ }
++
++ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
++ if (ret) {
++ dev_err(dev, "failed to initialize Gemini PHY\n");
++ return ret;
++ }
++
++ dev_info(dev, "initialized Gemini PHY\n");
++ return 0;
++}
++
+ /**
+ * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
+ *
+@@ -5662,6 +5732,12 @@ static int fotg210_hcd_probe(struct plat
+
+ fotg210_init(fotg210);
+
++ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
++ retval = fotg210_gemini_init(dev, hcd);
++ if (retval)
++ goto failed_dis_clk;
++ }
++
+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
+ if (retval) {
+ dev_err(dev, "failed to add hcd with err %d\n", retval);
--- /dev/null
+From dd62aee5d2d24199e71e745544e49a1a8b3c6f7a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 21 Apr 2017 20:50:22 +0200
+Subject: [PATCH 31/31] ARM: dts: Add the FOTG210 USB host to Gemini
+
+This adds the FOTG210 USB host controller to the Gemini
+device trees. In the main SoC DTSI it is flagged as disabled
+and then it is selectively enabled on the devices that utilize
+it (these per-platform enablements are done on the out-of-tree
+OpenWrt patch set). It is not enabled on the Itian SquareOne
+NAS/router since this instead has a VIA host controller
+soldered on the PCI port, and can gate off these USB host
+controllers.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+USB maintainers: I will merge this through the ARM SoC tree,
+the patch is only included in the series for context.
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 8 ++++++++
+ arch/arm/boot/dts/gemini-nas4220b.dts | 8 ++++++++
+ arch/arm/boot/dts/gemini-rut1xx.dts | 20 ++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd111.dts | 20 ++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 21 +++++++++++++++++++++
+ arch/arm/boot/dts/gemini.dtsi | 26 ++++++++++++++++++++++++++
+ 6 files changed, 103 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -303,5 +303,13 @@
+ };
+ };
+ };
++
++ usb@68000000 {
++ status = "okay";
++ };
++
++ usb@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -146,5 +146,13 @@
+ ata@63000000 {
+ status = "okay";
+ };
++
++ usb@68000000 {
++ status = "okay";
++ };
++
++ usb@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-rut1xx.dts
++++ b/arch/arm/boot/dts/gemini-rut1xx.dts
+@@ -114,5 +114,25 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
++
++ ethernet@60000000 {
++ status = "okay";
++
++ ethernet-port@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-port@1 {
++ /* Not used in this platform */
++ };
++ };
++
++ usb@68000000 {
++ status = "okay";
++ };
++
++ usb@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -160,5 +160,25 @@
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+ };
++
++ ethernet@60000000 {
++ status = "okay";
++
++ ethernet-port@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-port@1 {
++ /* Not used in this platform */
++ };
++ };
++
++ usb@68000000 {
++ status = "okay";
++ };
++
++ usb@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -165,5 +165,26 @@
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+ };
++
++ ethernet@60000000 {
++ status = "okay";
++
++ ethernet-port@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-port@1 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++ };
++
++ usb@68000000 {
++ status = "okay";
++ };
++
++ usb@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -411,5 +411,31 @@
+ #size-cells = <0>;
+ status = "disabled";
+ };
++
++ usb@68000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x68000000 0x1000>;
++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_USB0>;
++ clocks = <&syscon GEMINI_CLK_GATE_USB0>;
++ clock-names = "PCLK";
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_default_pins>;
++ syscon = <&syscon>;
++ status = "disabled";
++ };
++
++ usb@69000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x69000000 0x1000>;
++ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_USB1>;
++ clocks = <&syscon GEMINI_CLK_GATE_USB1>;
++ clock-names = "PCLK";
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_default_pins>;
++ syscon = <&syscon>;
++ status = "disabled";
++ };
+ };
+ };
--- /dev/null
+From 731a2896e11b4e6a8d252e6c14edb1b09dbfcd46 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+Date: Sat, 14 Apr 2018 18:49:57 +0200
+Subject: [PATCH 1/2] usb: host: fotg2: restart hcd after port reset
+
+on Gemini SoC FOTG2 stalls after port reset
+rerstart the hcd.
+
+Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
+---
+ drivers/usb/host/fotg210-hcd.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -1658,6 +1658,10 @@ static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ /* see what we found out */
+ temp = check_reset_complete(fotg210, wIndex, status_reg,
+ fotg210_readl(fotg210, status_reg));
++
++ /* restart schedule */
++ fotg210->command |= CMD_RUN;
++ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
+ }
+
+ if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
--- /dev/null
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -115,6 +115,14 @@
+ reg = <0x00fe0000 0x00020000>;
+ read-only;
+ };
++ firmware@20000 {
++ label = "firmware";
++ reg = <0x00020000 0x00f00000>;
++ };
++ rootfs@320000 {
++ label = "rootfs";
++ reg = <0x00320000 0x00c00000>;
++ };
+ };
+
+ syscon: syscon@40000000 {
--- /dev/null
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -137,6 +137,47 @@
+ groups = "gpio1dgrp";
+ };
+ };
++ pinctrl-gmii {
++ mux {
++ function = "gmii";
++ groups = "gmii_gmac0_grp";
++ };
++ conf0 {
++ pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV";
++ skew-delay = <0>;
++ };
++ conf1 {
++ pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC";
++ skew-delay = <15>;
++ };
++ conf2 {
++ pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN";
++ skew-delay = <7>;
++ };
++ conf3 {
++ pins = "U8 GMAC0 TXC";
++ skew-delay = <11>;
++ };
++ conf4 {
++ pins = "V11 GMAC1 TXC";
++ skew-delay = <10>;
++ };
++ conf5 {
++ pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
++ "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
++ "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
++ "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
++ "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
++ "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
++ "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
++ "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
++ skew-delay = <7>;
++ };
++ conf6 {
++ groups = "gmii_gmac0_grp";
++ drive-strength = <16>;
++ };
++ };
+ };
+ };
+
+@@ -151,6 +192,18 @@
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
+
++ ethernet@60000000 {
++ status = "okay";
++
++ gmac0: ethernet-port@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ gmac1: ethernet-port@1 {
++ status = "disabled";
++ };
++ };
++
+ ata@63000000 {
+ status = "okay";
+ };
--- /dev/null
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -208,6 +208,10 @@
+ status = "okay";
+ };
+
++ ata@63400000 {
++ status = "okay";
++ };
++
+ usb@68000000 {
+ status = "okay";
+ };
--- /dev/null
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -217,7 +217,7 @@
+ };
+
+ usb@69000000 {
+- status = "okay";
++ status = "disabled";
+ };
+ };
+ };
--- /dev/null
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1013,9 +1013,9 @@ static int geth_resize_freeq(struct gemi
+ int ret;
+
+ if (netdev->dev_id == 0)
+- other_netdev = geth->port1->netdev;
++ other_netdev = (geth->port1)? geth->port1->netdev : NULL;
+ else
+- other_netdev = geth->port0->netdev;
++ other_netdev = (geth->port0)? geth->port0->netdev : NULL;
+
+ if (other_netdev && netif_running(other_netdev))
+ return -EBUSY;
+@@ -2510,6 +2510,8 @@ static int gemini_ethernet_probe(struct
+ if (IS_ERR(geth->base))
+ return PTR_ERR(geth->base);
+ geth->dev = dev;
++ geth->port0 = NULL;
++ geth->port1 = NULL;
+
+ /* Wait for ports to stabilize */
+ do {
projects / openwrt / staging / hauke.git / commitdiff