clk: tegra: Implement memory-controller clock

The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 290f9c1a37498ccf16ae0b09804ca15e722a2da2..59a5714dfe18c237323821027ccae5bb59916a38 100644 (file)
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name,
 
        return clk;
 }
+
+static const struct clk_div_table mc_div_table[] = {
+       { .val = 0, .div = 2 },
+       { .val = 1, .div = 1 },
+       { .val = 0, .div = 0 },
+};
+
+struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
+                                 void __iomem *reg, spinlock_t *lock)
+{
+       return clk_register_divider_table(NULL, name, parent_name, 0, reg,
+                                         16, 1, 0, mc_div_table, lock);
+}

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index f760f31d05c40feadb7db666f5e8cf4dd2871e58..0b03d2cf7264f7d42dafb84fd83bb29e18f420a1 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock);
 static DEFINE_SPINLOCK(pll_d2_lock);
 static DEFINE_SPINLOCK(pll_u_lock);
 static DEFINE_SPINLOCK(pll_re_lock);
+static DEFINE_SPINLOCK(emc_lock);
 
 static struct div_nmp pllxc_nmp = {
        .divm_shift = 0,
@@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
                               ARRAY_SIZE(mux_pllmcp_clkm),
                               CLK_SET_RATE_NO_REPARENT,
                               clk_base + CLK_SOURCE_EMC,
-                              29, 3, 0, NULL);
+                              29, 3, 0, &emc_lock);
+
+       clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+                                   &emc_lock);
+       clks[TEGRA114_CLK_MC] = clk;
 
        for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
                data = &tegra_periph_clk_list[i];

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index e3a85842ce0c05890351f49f4d4a6c330812b9ab..f5f9baca7bb621924d14ff4d9364d18580e0fbc2 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock);
 static DEFINE_SPINLOCK(pll_e_lock);
 static DEFINE_SPINLOCK(pll_re_lock);
 static DEFINE_SPINLOCK(pll_u_lock);
+static DEFINE_SPINLOCK(emc_lock);
 
 /* possible OSC frequencies in Hz */
 static unsigned long tegra124_input_freq[] = {
@@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
        clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
                               ARRAY_SIZE(mux_pllmcp_clkm), 0,
                               clk_base + CLK_SOURCE_EMC,
-                              29, 3, 0, NULL);
+                              29, 3, 0, &emc_lock);
+
+       clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+                                   &emc_lock);
+       clks[TEGRA124_CLK_MC] = clk;
 
        /* cml0 */
        clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index dace2b1b5ae66dafab4fe4639e6291872491119d..41272dcc9e225758da291018dc71bf921f85be8f 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context {
 static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
+static DEFINE_SPINLOCK(emc_lock);
+
 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,  \
                            _clk_num, _gate_flags, _clk_id)     \
        TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
@@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void)
                               ARRAY_SIZE(mux_pllmcp_clkm),
                               CLK_SET_RATE_NO_REPARENT,
                               clk_base + CLK_SOURCE_EMC,
-                              30, 2, 0, NULL);
+                              30, 2, 0, &emc_lock);
        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
                                    57, periph_clk_enb_refcnt);
        clks[TEGRA20_CLK_EMC] = clk;
 
+       clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+                                   &emc_lock);
+       clks[TEGRA20_CLK_MC] = clk;
+
        /* dsi */
        clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
                                    48, periph_clk_enb_refcnt);

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 5bbacd01094f3770fcd3161e733070ea3412b97c..4b9d8bd3d0bfdd8e93f0436ea3bd0f016d5091fb 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -177,6 +177,7 @@ static unsigned long input_freq;
 
 static DEFINE_SPINLOCK(cml_lock);
 static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(emc_lock);
 
 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,  \
                            _clk_num, _gate_flags, _clk_id)     \
@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)
                               ARRAY_SIZE(mux_pllmcp_clkm),
                               CLK_SET_RATE_NO_REPARENT,
                               clk_base + CLK_SOURCE_EMC,
-                              30, 2, 0, NULL);
+                              30, 2, 0, &emc_lock);
        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
                                    57, periph_clk_enb_refcnt);
        clks[TEGRA30_CLK_EMC] = clk;
 
+       clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+                                   &emc_lock);
+       clks[TEGRA30_CLK_MC] = clk;
+
        /* cml0 */
        clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
                                0, 0, &cml_lock);

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 16ec8d6bb87f287724ff53a362b8c39de2880193..4e458aa8d45c19e6ec1ee3cf9050cfc044cdec28 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name,
                const char *parent_name, void __iomem *reg,
                unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
                u8 frac_width, spinlock_t *lock);
+struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
+                                 void __iomem *reg, spinlock_t *lock);
 
 /*
  * Tegra PLL:

diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index fc12621fb4329188ed6a6a9da2efe8b7da3603a7..534c03f8ad72bc23675e0a4fe7761b2257f1b741 100644 (file)
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
 #define TEGRA114_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA114_CLK_MC 32
 /* 33 */
 #define TEGRA114_CLK_APBDMA 34
 /* 35 */

diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 6bac637fd635d16717b027b136ba70bba465276b..af9bc9a3ddbc561840b60f6f5416f19f846e8567 100644 (file)
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -48,7 +48,7 @@
 #define TEGRA124_CLK_I2S0 30
 /* 31 */
 
-/* 32 */
+#define TEGRA124_CLK_MC 32
 /* 33 */
 #define TEGRA124_CLK_APBDMA 34
 /* 35 */

diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index 9406207cfac8715b2545a8e77ae8bc7866e838fb..04500b243a4d89be0731a326baca289ee4efbd29 100644 (file)
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
 /* 30 */
 #define TEGRA20_CLK_CACHE2 31
 
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
 #define TEGRA20_CLK_AHBDMA 33
 #define TEGRA20_CLK_APBDMA 34
 /* 35 */