drm/i915: Implement WaDisableSDEUnitClockGating:bdw
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 27 Feb 2014 19:59:02 +0000 (21:59 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 5 Mar 2014 20:30:33 +0000 (21:30 +0100)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index d11a9ea5884d5136f93451ab977c7d547757e9d9..c913ca5c3b392aaa32a1a9d252a0c6eafc273bb4 100644 (file)
 #define GEN7_UCGCTL4                           0x940c
 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE      (1<<25)
 
+#define GEN8_UCGCTL6                           0x9430
+#define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE      (1<<14)
+
 #define GEN6_RPNSWREQ                          0xA008
 #define   GEN6_TURBO_DISABLE                   (1<<31)
 #define   GEN6_FREQUENCY(x)                    ((x)<<25)
index 739eabc814e9119a9ed4f6989bfb36432d9150b9..5819f5c92554cf294ad4988feb5a0f61d2a19759 100644 (file)
@@ -4870,6 +4870,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 
        I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
                   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+
+       /* WaDisableSDEUnitClockGating:bdw */
+       I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+                  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)