ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x

SVN-Revision: 33362

diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
index 289ec6d29616873c201e203275d35397613e96ea..bb0924c430d736d323485cb4122293c66c5c1a80 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
+++ b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
@@ -38,7 +38,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 +             QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
 +
 +      cpu_pll = nint * ath79_ref_clk.rate / ref_div;
-+      cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
++      cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
 +      cpu_pll /= (1 << out_div);
 +
 +      pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@@ -52,7 +52,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 +             QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
 +
 +      ddr_pll = nint * ath79_ref_clk.rate / ref_div;
-+      ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
++      ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
 +      ddr_pll /= (1 << out_div);
 +
 +      clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);