drm/amdgpu: remove gart.table_addr

We can easily figure out the address on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index f5cb5e2856c171656fce7c76c8d8964f7d12b1f1..11fea28f8ad30da94a18a28763a498bb5f84868e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -157,7 +157,6 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
        if (r)
                amdgpu_bo_unpin(adev->gart.bo);
        amdgpu_bo_unreserve(adev->gart.bo);
-       adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        return r;
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index d7b7c2d408d5911c6594ef72a310c774c79761eb..9ff62887e4e32cd0378295720e7517d74b035efd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -40,7 +40,6 @@ struct amdgpu_bo;
 #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
 
 struct amdgpu_gart {
-       u64                             table_addr;
        struct amdgpu_bo                *bo;
        void                            *ptr;
        unsigned                        num_gpu_pages;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b4333f60ed8be0f3bc09ac05285e66bcbb61c690..e7f73deed975ba6e1ad29cc67cc2c8f3f1f67cc3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1988,7 +1988,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
        src_addr = num_dw * 4;
        src_addr += job->ibs[0].gpu_addr;
 
-       dst_addr = adev->gart.table_addr;
+       dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
        amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
                                dst_addr, num_bytes);
@@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
                return r;
 
        if (vm_needs_flush) {
-               job->vm_pd_addr = adev->gart.table_addr;
+               job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
                job->vm_needs_flush = true;
        }
        if (resv) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index acfbd2d749cf187ee83bcd186c1f5edb9b4a5c4b..2baab7e69ef5773e9e1c54c133bcff15aef39ab0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -37,11 +37,10 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-       uint64_t value;
+       uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
 
-       BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-       value = adev->gart.table_addr - adev->gmc.vram_start
-               + adev->vm_manager.vram_base_offset;
+       BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+       value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
        value &= 0x0000FFFFFFFFF000ULL;
        value |= 0x1; /*valid bit*/
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b4302aaa1c14f3126c4bd9c6ca161854348aa2ec..543287e5d67bf49b02f6ac0a5b52232123e15a04 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -494,6 +494,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
+       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        int r, i;
        u32 field;
 
@@ -532,7 +533,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page_addr >> 12));
        WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -556,10 +557,10 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
        for (i = 1; i < 16; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
                else
                        WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
        }
 
        /* enable context1-15 */
@@ -579,7 +580,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
        gmc_v6_0_flush_gpu_tlb(adev, 0);
        dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
-                (unsigned long long)adev->gart.table_addr);
+                (unsigned long long)table_addr);
        adev->gart.ready = true;
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b41b8515670dd13bce392a401d4598c811fe29ba..c88708abe016946ef83a797be548144771006774 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -602,6 +602,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 {
+       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        int r, i;
        u32 tmp, field;
 
@@ -643,7 +644,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page_addr >> 12));
        WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -667,10 +668,10 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        for (i = 1; i < 16; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
                else
                        WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
        }
 
        /* enable context1-15 */
@@ -697,7 +698,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        gmc_v7_0_flush_gpu_tlb(adev, 0);
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
-                (unsigned long long)adev->gart.table_addr);
+                (unsigned long long)table_addr);
        adev->gart.ready = true;
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d2fc97a2ab0094f58f72f004bc1471679cbfb25f..8213ea1a6cbc7d5a3156e5facfbe906bd70cc8ff 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -807,6 +807,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 {
+       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
        int r, i;
        u32 tmp, field;
 
@@ -864,7 +865,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+       WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page_addr >> 12));
        WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -888,10 +889,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        for (i = 1; i < 16; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
                else
                        WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-                              adev->gart.table_addr >> 12);
+                              table_addr >> 12);
        }
 
        /* enable context1-15 */
@@ -919,7 +920,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        gmc_v8_0_flush_gpu_tlb(adev, 0);
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
-                (unsigned long long)adev->gart.table_addr);
+                (unsigned long long)table_addr);
        adev->gart.ready = true;
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c9550b11e19a216c2f585ef01743e3866d8a697f..dc48e19d01f8389fdb69c19607fc3ab6606eef18 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1106,7 +1106,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
-                (unsigned long long)adev->gart.table_addr);
+                (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
        adev->gart.ready = true;
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index e70a0d4d6db4111a59239accef4d47d0d6676d72..800ec4687f13b4c4c101c10b60e027cb9d16854e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -47,11 +47,10 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
 
 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-       uint64_t value;
+       uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
 
-       BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-       value = adev->gart.table_addr - adev->gmc.vram_start +
-               adev->vm_manager.vram_base_offset;
+       BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+       value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
        value &= 0x0000FFFFFFFFF000ULL;
        value |= 0x1; /* valid bit */