drm/armada: clean up SPU_ADV_REG

Rather than writing all bits of SPU_ADV_REG on modeset, only write
what we need to change, and initialise the register in the variant
initialisation.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/drivers/gpu/drm/armada/armada_510.c b/drivers/gpu/drm/armada/armada_510.c
index 41a784f5a5e64df3feabcc0ad3e1053f64a29aaa..9a4fbb6a24b8f1258ce67431d167633d5b69a6b9 100644 (file)
--- a/drivers/gpu/drm/armada/armada_510.c
+++ b/drivers/gpu/drm/armada/armada_510.c
@@ -27,6 +27,10 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
        /* Lower the watermark so to eliminate jitter at higher bandwidths */
        armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
 
+       /* Initialise SPU register */
+       writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
+                      dcrtc->base + LCD_SPU_ADV_REG);
+
        return 0;
 }
 
@@ -77,7 +81,6 @@ static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
 
 const struct armada_variant armada510_ops = {
        .has_spu_adv_reg = true,
-       .spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
        .init = armada510_crtc_init,
        .compute_clock = armada510_crtc_compute_clock,
 };

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 9ad966caf08cc6fa75149445e94ea6ece64e1a48..80d34a4b7d4168a7e1b82d4096999db41d6e09e9 100644 (file)
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -463,17 +463,15 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
                                    adj->crtc_htotal;
        dcrtc->v[1].spu_v_porch = tm << 16 | bm;
        val = adj->crtc_hsync_start;
-       dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
-               dcrtc->variant->spu_adv_reg;
+       dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
 
        if (interlaced) {
                /* Odd interlaced frame */
+               val -= adj->crtc_htotal / 2;
+               dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
                dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
                                                (1 << 16);
                dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
-               val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
-               dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
-                       dcrtc->variant->spu_adv_reg;
        } else {
                dcrtc->v[0] = dcrtc->v[1];
        }
@@ -486,11 +484,10 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
        armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
                           LCD_SPUT_V_H_TOTAL);
 
-       if (dcrtc->variant->has_spu_adv_reg) {
+       if (dcrtc->variant->has_spu_adv_reg)
                armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
                                     ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
                                     ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
-       }
 
        val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
        armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);

diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada/armada_drm.h
index 64f1c8836078cf28788d66e09eb4466857c1848a..a6f919b0084c6ff1de455c049cfc2e330cddb94c 100644 (file)
--- a/drivers/gpu/drm/armada/armada_drm.h
+++ b/drivers/gpu/drm/armada/armada_drm.h
@@ -42,7 +42,6 @@ struct armada_private;
 
 struct armada_variant {
        bool has_spu_adv_reg;
-       uint32_t spu_adv_reg;
        int (*init)(struct armada_crtc *, struct device *);
        int (*compute_clock)(struct armada_crtc *,
                             const struct drm_display_mode *,