MIPS: KVM: Use mipsregs.h defs for config registers

Convert MIPS KVM guest register state initialisation to use the standard
<asm/mipsregs.h> register field definitions for Config registers, and
drop the custom definitions in kvm_host.h which it was using before.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 6c43c782bdfad17762e903c25ccca1fe2059e31b..b0773c6d622fa58fc05212f56c506c17b489ceaa 100644 (file)
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -205,73 +205,6 @@ struct mips_coproc {
 #define MIPS_CP0_CONFIG4_SEL   4
 #define MIPS_CP0_CONFIG5_SEL   5
 
-/* Config0 register bits */
-#define CP0C0_M                        31
-#define CP0C0_K23              28
-#define CP0C0_KU               25
-#define CP0C0_MDU              20
-#define CP0C0_MM               17
-#define CP0C0_BM               16
-#define CP0C0_BE               15
-#define CP0C0_AT               13
-#define CP0C0_AR               10
-#define CP0C0_MT               7
-#define CP0C0_VI               3
-#define CP0C0_K0               0
-
-/* Config1 register bits */
-#define CP0C1_M                        31
-#define CP0C1_MMU              25
-#define CP0C1_IS               22
-#define CP0C1_IL               19
-#define CP0C1_IA               16
-#define CP0C1_DS               13
-#define CP0C1_DL               10
-#define CP0C1_DA               7
-#define CP0C1_C2               6
-#define CP0C1_MD               5
-#define CP0C1_PC               4
-#define CP0C1_WR               3
-#define CP0C1_CA               2
-#define CP0C1_EP               1
-#define CP0C1_FP               0
-
-/* Config2 Register bits */
-#define CP0C2_M                        31
-#define CP0C2_TU               28
-#define CP0C2_TS               24
-#define CP0C2_TL               20
-#define CP0C2_TA               16
-#define CP0C2_SU               12
-#define CP0C2_SS               8
-#define CP0C2_SL               4
-#define CP0C2_SA               0
-
-/* Config3 Register bits */
-#define CP0C3_M                        31
-#define CP0C3_ISA_ON_EXC       16
-#define CP0C3_ULRI             13
-#define CP0C3_DSPP             10
-#define CP0C3_LPA              7
-#define CP0C3_VEIC             6
-#define CP0C3_VInt             5
-#define CP0C3_SP               4
-#define CP0C3_MT               2
-#define CP0C3_SM               1
-#define CP0C3_TL               0
-
-/* MMU types, the first four entries have the same layout as the
-   CP0C0_MT field.  */
-enum mips_mmu_types {
-       MMU_TYPE_NONE,
-       MMU_TYPE_R4000,
-       MMU_TYPE_RESERVED,
-       MMU_TYPE_FMT,
-       MMU_TYPE_R3000,
-       MMU_TYPE_R6000,
-       MMU_TYPE_R8000
-};
-
 /* Resume Flags */
 #define RESUME_FLAG_DR         (1<<0)  /* Reload guest nonvolatile state? */
 #define RESUME_FLAG_HOST       (1<<1)  /* Resume host? */

diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c
index 1dc003ddca913f48f047abac90cdf664859f78b9..00e8dc3d36cb1c99013d31905db0d2ad18b82864 100644 (file)
--- a/arch/mips/kvm/trap_emul.c
+++ b/arch/mips/kvm/trap_emul.c
@@ -440,8 +440,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
         * host.
         */
        config = read_c0_config() & MIPS_CONF_AR;
-       config |= MIPS_CONF_M | (0x3 << CP0C0_K0) |
-               (MMU_TYPE_R4000 << CP0C0_MT);
+       config |= MIPS_CONF_M | CONF_CM_CACHABLE_NONCOHERENT | MIPS_CONF_MT_TLB;
 #ifdef CONFIG_CPU_BIG_ENDIAN
        config |= CONF_BE;
 #endif
@@ -457,9 +456,8 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
        config1 |= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25);
 
        /* We unset some bits that we aren't emulating */
-       config1 &=
-           ~((1 << CP0C1_C2) | (1 << CP0C1_MD) | (1 << CP0C1_PC) |
-             (1 << CP0C1_WR) | (1 << CP0C1_CA));
+       config1 &= ~(MIPS_CONF1_C2 | MIPS_CONF1_MD | MIPS_CONF1_PC |
+                    MIPS_CONF1_WR | MIPS_CONF1_CA);
        kvm_write_c0_guest_config1(cop0, config1);
 
        /* Have config3, no tertiary/secondary caches implemented */