board: fsl: lx2160ardb: invert AQR107 pins polarity
authorFlorin Chiculita <florinlaurentiu.chiculita@nxp.com>
Mon, 22 Apr 2019 08:57:47 +0000 (11:57 +0300)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Wed, 22 May 2019 06:54:24 +0000 (12:24 +0530)
AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
board/freescale/lx2160a/lx2160a.c
include/configs/lx2160ardb.h

index 3875d045438eb55671543860c9744e58e13f0820..6109b280c6815ffb767feff0efefa559c6604c85 100644 (file)
@@ -449,12 +449,20 @@ unsigned long get_board_ddr_clk(void)
 
 int board_init(void)
 {
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+       u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
 #ifdef CONFIG_ENV_IS_NOWHERE
        gd->env_addr = (ulong)&default_environment[0];
 #endif
 
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+       /* invert AQR107 IRQ pins polarity */
+       out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
 #ifdef CONFIG_FSL_CAAM
        sec_init();
 #endif
index 972bb5e102bcbb2c26ef3c09dfd3c702ba4f67d5..c6bacb65ec0864d23c77e2635d2339462a88abda 100644 (file)
@@ -60,6 +60,7 @@
 
 #define AQR107_PHY_ADDR1       0x04
 #define AQR107_PHY_ADDR2       0x05
+#define AQR107_IRQ_MASK                0x0C
 
 #define CORTINA_NO_FW_UPLOAD
 #define CORTINA_PHY_ADDR1      0x0