AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
}
+static void ar9003_mci_stat_setup(struct ath_hw *ah)
+{
+ struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+
+ if (!AR_SREV_9565(ah))
+ return;
+
+ if (mci->config & ATH_MCI_CONFIG_MCI_STAT_DBG) {
+ REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
+ AR_MCI_DBG_CNT_CTRL_ENABLE, 1);
+ REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
+ AR_MCI_DBG_CNT_CTRL_BT_LINKID,
+ MCI_STAT_ALL_BT_LINKID);
+ } else {
+ REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
+ AR_MCI_DBG_CNT_CTRL_ENABLE, 0);
+ }
+}
+
static void ar9003_mci_set_btcoex_ctrl_9565_1ANT(struct ath_hw *ah)
{
u32 regval;
mci->ready = true;
ar9003_mci_prep_interface(ah);
+ ar9003_mci_stat_setup(ah);
- if (AR_SREV_9565(ah))
- REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
- AR_MCI_DBG_CNT_CTRL_ENABLE, 0);
if (en_int)
ar9003_mci_enable_interrupt(ah);
#define AR_MCI_MISC 0x1a74
#define AR_MCI_MISC_HW_FIX_EN 0x00000001
#define AR_MCI_MISC_HW_FIX_EN_S 0
+
#define AR_MCI_DBG_CNT_CTRL 0x1a78
#define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001
#define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0
+#define AR_MCI_DBG_CNT_CTRL_BT_LINKID 0x000007f8
+#define AR_MCI_DBG_CNT_CTRL_BT_LINKID_S 3
+
+#define MCI_STAT_ALL_BT_LINKID 0xffff
#define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \
AR_MCI_INTERRUPT_RX_INVALID_HDR | \