drm/i915: Split color mgmt based on single vs. double buffered registers

Split the color management hooks along the single vs. double
buffered registers line. Of the currently programmed registers
GAMMA_MODE and the ilk+ pipe CSC are double buffered, the
LUTS and CHV CGM block are single buffered.

The double buffered register will be programmed during the
normal pipe update with evasion, and also during pipe enable
so that the settings will already be correct when the pipe
starts up before the planes are enabled.

The single buffered registers are currently programmed before
the vblank evade. Which is totally wrong, but we'll correct
that later.

v2: Add some docs to explain the two vfuncs (Matt,Uma)
    Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-6-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ca96376651b1b6025d5479b65eb90fbc3ee9ef9..08d75d57b34e0f7e9a63b49f787debf900271d46 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,7 +323,19 @@ struct drm_i915_display_funcs {
        /* display clock increase/decrease */
        /* pll clock increase/decrease */
 
-       void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
+       /*
+        * Program double buffered color management registers during
+        * vblank evasion. The registers should then latch during the
+        * next vblank start, alongside any other double buffered registers
+        * involved with the same commit.
+        */
+       void (*color_commit)(const struct intel_crtc_state *crtc_state);
+       /*
+        * Load LUTs (and other single buffered color management
+        * registers). Will (hopefully) be called during the vblank
+        * following the latching of any double buffered registers
+        * involved with the same commit.
+        */
        void (*load_luts)(const struct intel_crtc_state *crtc_state);
 };
 

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 171dff60d62f348caaa4ca9c33c8f592ac3487cb..c364cb7cb14c3d23f7e3c2381066f9fc6ac649f5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -304,14 +304,6 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
        I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 }
 
-void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
-{
-       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-
-       if (dev_priv->display.load_csc_matrix)
-               dev_priv->display.load_csc_matrix(crtc_state);
-}
-
 /* Loads the legacy palette/gamma unit for the CRTC. */
 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
                                    const struct drm_property_blob *blob)
@@ -359,6 +351,16 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
        i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 }
 
+static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+       I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
+
+       ilk_load_csc_matrix(crtc_state);
+}
+
 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
 static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
 {
@@ -376,8 +378,6 @@ static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
                reenable_ips = true;
        }
 
-       I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
-
        i9xx_load_luts(crtc_state);
 
        if (reenable_ips)
@@ -485,8 +485,6 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
                 */
                I915_WRITE(PREC_PAL_INDEX(pipe), 0);
        }
-
-       I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -539,8 +537,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
                 */
                I915_WRITE(PREC_PAL_INDEX(pipe), 0);
        }
-
-       I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
 static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
@@ -551,10 +547,9 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
        const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
        enum pipe pipe = crtc->pipe;
 
+       cherryview_load_csc_matrix(crtc_state);
+
        if (crtc_state_is_legacy_gamma(crtc_state)) {
-               /* Turn off degamma/gamma on CGM block. */
-               I915_WRITE(CGM_PIPE_MODE(pipe),
-                          (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
                i9xx_load_luts_internal(crtc_state, gamma_lut);
                return;
        }
@@ -595,11 +590,6 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
                }
        }
 
-       I915_WRITE(CGM_PIPE_MODE(pipe),
-                  (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
-                  (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-                  (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
-
        /*
         * Also program a linear LUT in the legacy block (behind the
         * CGM block).
@@ -614,6 +604,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
        dev_priv->display.load_luts(crtc_state);
 }
 
+void intel_color_commit(const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+       if (dev_priv->display.color_commit)
+               dev_priv->display.color_commit(crtc_state);
+}
+
 static int check_lut_size(const struct drm_property_blob *lut, int expected)
 {
        int len;
@@ -675,18 +673,17 @@ void intel_color_init(struct intel_crtc *crtc)
        drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
        if (IS_CHERRYVIEW(dev_priv)) {
-               dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
                dev_priv->display.load_luts = cherryview_load_luts;
        } else if (IS_HASWELL(dev_priv)) {
-               dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
                dev_priv->display.load_luts = haswell_load_luts;
+               dev_priv->display.color_commit = hsw_color_commit;
        } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
                   IS_BROXTON(dev_priv)) {
-               dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
                dev_priv->display.load_luts = broadwell_load_luts;
+               dev_priv->display.color_commit = hsw_color_commit;
        } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-               dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
                dev_priv->display.load_luts = glk_load_luts;
+               dev_priv->display.color_commit = hsw_color_commit;
        } else {
                dev_priv->display.load_luts = i9xx_load_luts;
        }

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index be5a73b6805addb9cc6042b888e6cda481005f93..63b61f61eccc35126f9cf7344270dcb82f327d54 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5779,6 +5779,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
         * clocks enabled
         */
        intel_color_load_luts(pipe_config);
+       intel_color_commit(pipe_config);
 
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
@@ -5888,8 +5889,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
        haswell_set_pipemisc(pipe_config);
 
-       intel_color_set_csc(pipe_config);
-
        intel_crtc->active = true;
 
        /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
@@ -5908,6 +5907,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
         * clocks enabled
         */
        intel_color_load_luts(pipe_config);
+       intel_color_commit(pipe_config);
 
        if (INTEL_GEN(dev_priv) >= 11)
                icl_set_pipe_chicken(intel_crtc);
@@ -6245,8 +6245,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
        i9xx_set_pipeconf(pipe_config);
 
-       intel_color_set_csc(pipe_config);
-
        intel_crtc->active = true;
 
        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6266,6 +6264,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
        i9xx_pfit_enable(pipe_config);
 
        intel_color_load_luts(pipe_config);
+       intel_color_commit(pipe_config);
 
        dev_priv->display.initial_watermarks(old_intel_state,
                                             pipe_config);
@@ -6322,6 +6321,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
        i9xx_pfit_enable(pipe_config);
 
        intel_color_load_luts(pipe_config);
+       intel_color_commit(pipe_config);
 
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(old_intel_state,
@@ -13742,10 +13742,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 
        if (!modeset &&
            (intel_cstate->base.color_mgmt_changed ||
-            intel_cstate->update_pipe)) {
-               intel_color_set_csc(intel_cstate);
+            intel_cstate->update_pipe))
                intel_color_load_luts(intel_cstate);
-       }
 
        /* Perform vblank evasion around commit operation */
        intel_pipe_update_start(intel_cstate);
@@ -13753,6 +13751,10 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
        if (modeset)
                goto out;
 
+       if (intel_cstate->base.color_mgmt_changed ||
+           intel_cstate->update_pipe)
+               intel_color_commit(intel_cstate);
+
        if (intel_cstate->update_pipe)
                intel_update_pipe_config(old_intel_cstate, intel_cstate);
        else if (INTEL_GEN(dev_priv) >= 9)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2c299456fdbd4ead76863745f1b0d357ea5696db..aa003ab8c4aa5df43d343fc7e43b496f64d125d8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2389,7 +2389,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 /* intel_color.c */
 void intel_color_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
-void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
+void intel_color_commit(const struct intel_crtc_state *crtc_state);
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
 
 /* intel_lspcon.c */