x86/cpufeature: Enable RING3MWAIT for Knights Mill

Enable ring 3 MONITOR/MWAIT for Intel Xeon Phi codenamed Knights Mill. We
can't guarantee that this (KNM) will be the last CPU model that needs this
hack.  But, we do recognize that this is far from optimal, and there is an
effort to ensure we don't keep doing extending this hack forever.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Cc: Piotr.Luc@intel.com
Cc: dave.hansen@linux.intel.com
Link: http://lkml.kernel.org/r/1484918557-15481-6-git-send-email-grzegorz.andrejczuk@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index da2401a4b0f4b9a8645d0ec0be98c2a2eaacca3f..a4c4ff9b27e4d4de70afff579806de6c5d2cae05 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -79,8 +79,15 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
         * Ring 3 MONITOR/MWAIT feature cannot be detected without
         * cpu model and family comparison.
         */
-       if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+       if (c->x86 != 6)
                return;
+       switch (c->x86_model) {
+       case INTEL_FAM6_XEON_PHI_KNL:
+       case INTEL_FAM6_XEON_PHI_KNM:
+               break;
+       default:
+               return;
+       }
 
        if (ring3mwait_disabled) {
                msr_clear_bit(MSR_MISC_FEATURE_ENABLES,