#define CAYMAN_RING_TYPE_DMA1_INDEX 4
/* R600+ */
- #define R600_RING_TYPE_UVD_INDEX 5
+ #define R600_RING_TYPE_UVD_INDEX 5
+
+ /* TN+ */
+ #define TN_RING_TYPE_VCE1_INDEX 6
+ #define TN_RING_TYPE_VCE2_INDEX 7
+
+ /* max number of rings */
+ #define RADEON_NUM_RINGS 8
+
+ /* number of hw syncs before falling back on blocking */
+ #define RADEON_NUM_SYNCS 4
+/* number of hw syncs before falling back on blocking */
+#define RADEON_NUM_SYNCS 4
+
/* hardcode those limit for now */
#define RADEON_VA_IB_OFFSET (1 << 20)
#define RADEON_VA_RESERVED_SIZE (8 << 20)