Revert "ARM: shmobile: r8a7790: Add SSI clocks in device tree"
authorSimon Horman <horms+renesas@verge.net.au>
Thu, 26 Dec 2013 05:15:47 +0000 (14:15 +0900)
committerSimon Horman <horms+renesas@verge.net.au>
Thu, 26 Dec 2013 05:15:47 +0000 (14:15 +0900)
This reverts commit 6dea2c1ebc6fc43852fd6125d75a75da223ff707.

Unfortunately this commit prevents multiplatform from booting to
the point where a serial console is available. Revert it while
a solution is sought.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index c5417dafca0d5b6278dd1dc9884e83bc2d97c70e..a1791250bf4b354148961f867568a5879ff0cd43 100644 (file)
                        clock-output-names =
                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
                };
-               mstp10_clks: mstp10_clks@e6150998 {
-                       compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
-                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
-                       clocks = <&p_clk>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>;
-                       #clock-cells = <1>;
-                       renesas,clock-indices = <
-                               R8A7790_CLK_SSI R8A7790_CLK_SSI9 R8A7790_CLK_SSI8
-                               R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
-                               R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2
-                               R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
-                       >;
-                       clock-output-names =
-                               "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
-                               "ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
-               };
        };
 };
index dbb262a3e7a60b321ed09e6c68c1ce26c0f8ac3d..859e9be511d9251b7e7033a5a9489a9091237b5f 100644 (file)
 #define R8A7790_CLK_I2C1               30
 #define R8A7790_CLK_I2C0               31
 
-/* MSTP10 */
-#define R8A7790_CLK_SSI                        5
-#define R8A7790_CLK_SSI9               6
-#define R8A7790_CLK_SSI8               7
-#define R8A7790_CLK_SSI7               8
-#define R8A7790_CLK_SSI6               9
-#define R8A7790_CLK_SSI5               10
-#define R8A7790_CLK_SSI4               11
-#define R8A7790_CLK_SSI3               12
-#define R8A7790_CLK_SSI2               13
-#define R8A7790_CLK_SSI1               14
-#define R8A7790_CLK_SSI0               15
-
 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */