bcm281xx: add support for "USB OTG clock"
authorSteve Rae <srae@broadcom.com>
Tue, 9 Dec 2014 19:40:11 +0000 (11:40 -0800)
committerTom Rini <trini@ti.com>
Mon, 29 Dec 2014 21:31:23 +0000 (16:31 -0500)
enable this clock with the following:
  clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
arch/arm/cpu/armv7/bcm281xx/Makefile
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c [new file with mode: 0644]
arch/arm/cpu/armv7/kona-common/clk-stubs.c
arch/arm/include/asm/arch-bcm281xx/sysmap.h
arch/arm/include/asm/kona-common/clk.h

index bd867a271802fa32ea00b0836b63949086b4ccd7..f24aeb3826828fdc0d040c27712b099f4477085b 100644 (file)
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
 obj-y  += clk-sdio.o
 obj-y  += clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y  += clk-usb-otg.o
index d16b99fc23bc5ff36b9d291fe2e37813cedc4283..7e25255230abb44508a25380c3dcf346dca451a3 100644 (file)
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
        .gate           = SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
        .gate           = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+       .clk = {
+               .name = "usb_otg_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
        .clk = {
                .name = "sdio1_ahb_clk",
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
        CLK_LK(bsc2),
        CLK_LK(bsc3),
        /* Bus clocks */
+       CLK_LK(usb_otg_ahb),
        CLK_LK(sdio1_ahb),
        CLK_LK(sdio2_ahb),
        CLK_LK(sdio3_ahb),
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
new file mode 100644 (file)
index 0000000..1d7c5af
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+       char *ahbstr;
+
+       switch ((u32) base) {
+       case HSOTG_BASE_ADDR:
+               ahbstr = "usb_otg_ahb_clk";
+               break;
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       return clk_get_and_enable(ahbstr);
+}
index 338e0e4962fb0b996716ed44e99a16fc3c2c0d2f..fa10802620702a12a9367b4f9ff724d38aac1dab 100644 (file)
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
 {
        return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+       return 0;
+}
index 350e7f6b723059644e1b559db76ab1a4f485a426..93ebf3429a713e24ec58890982c03c8098e01b8b 100644 (file)
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR     0x38000000
 #define ESW_CONTRL_BASE_ADDR   0x38200000
 #define GPIO2_BASE_ADDR                0x35003000
+#define HSOTG_BASE_ADDR                0x3f120000
+#define HSOTG_CTRL_BASE_ADDR   0x3f130000
 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
 #define PMU_BSC_BASE_ADDR      0x3500d000
index 2c7e829994bae4767e6ede46ef43548af85a0aa9..a5e2fd9d6cc307f194b659b844600ac5670bb4dd 100644 (file)
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif