Add ddr interleaving suppport for MPC8572DS board

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 435893a4ec9bbcdea20fd2d895a08599296b1032..d66ede2d5d45b88dbba0e5592dc262c61e86a258 100644 (file)
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -39,42 +39,108 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
        }
 }
 
+typedef struct {
+       u32 datarate_mhz_low;
+       u32 datarate_mhz_high;
+       u32 n_ranks;
+       u32 clk_adjust;
+       u32 cpo;
+       u32 write_data_delay;
+       u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+       {
+       /*      memory controller 0                     */
+       /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
+       /*       mhz| mhz|ranks|adjst|    | delay|      */
+               {  0, 333,    2,    6,   7,    3,  0},
+               {334, 400,    2,    6,   9,    3,  0},
+               {401, 549,    2,    6,  11,    3,  0},
+               {550, 680,    2,    1,  10,    5,  0},
+               {681, 850,    2,    1,  12,    5,  1},
+               {  0, 333,    1,    6,   7,    3,  0},
+               {334, 400,    1,    6,   9,    3,  0},
+               {401, 549,    1,    6,  11,    3,  0},
+               {550, 680,    1,    1,  10,    5,  0},
+               {681, 850,    1,    1,  12,    5,  0}
+       },
+
+       {
+       /*      memory controller 1                     */
+       /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
+       /*       mhz| mhz|ranks|adjst|    | delay|      */
+               {  0, 333,    2,     6,  7,    3,  0},
+               {334, 400,    2,     6,  9,    3,  0},
+               {401, 549,    2,     6, 11,    3,  0},
+               {550, 680,    2,     1, 11,    6,  0},
+               {681, 850,    2,     1, 13,    6,  1},
+               {  0, 333,    1,     6,  7,    3,  0},
+               {334, 400,    1,     6,  9,    3,  0},
+               {401, 549,    1,     6, 11,    3,  0},
+               {550, 680,    1,     1, 11,    6,  0},
+               {681, 850,    1,     1, 13,    6,  0}
+       }
+};
+
 void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
 {
-       /*
-        * Factors to consider for clock adjust:
-        *      - number of chips on bus
-        *      - position of slot
-        *      - DDR1 vs. DDR2?
-        *      - ???
-        *
-        * This needs to be determined on a board-by-board basis.
-        *      0110    3/4 cycle late
-        *      0111    7/8 cycle late
-        */
-       popts->clk_adjust = 7;
+       const board_specific_parameters_t *pbsp =
+                               &(board_specific_parameters[ctrl_num][0]);
+       u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+                               sizeof(board_specific_parameters[0][0]);
+       u32 i;
+       ulong ddr_freq;
 
-       /*
-        * Factors to consider for CPO:
-        *      - frequency
-        *      - ddr1 vs. ddr2
+       /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+        * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+        * there are two dimms in the controller, set odt_rd_cfg to 3 and
+        * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
         */
-       popts->cpo_override = 10;
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i&1) {      /* odd CS */
+                       popts->cs_local_opts[i].odt_rd_cfg = 0;
+                       popts->cs_local_opts[i].odt_wr_cfg = 0;
+               } else {        /* even CS */
+                       if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+                               popts->cs_local_opts[i].odt_rd_cfg = 0;
+                               popts->cs_local_opts[i].odt_wr_cfg = 4;
+                       } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+                       popts->cs_local_opts[i].odt_rd_cfg = 3;
+                       popts->cs_local_opts[i].odt_wr_cfg = 3;
+                       }
+               }
+       }
 
-       /*
-        * Factors to consider for write data delay:
-        *      - number of DIMMs
-        *
-        * 1 = 1/4 clock delay
-        * 2 = 1/2 clock delay
-        * 3 = 3/4 clock delay
-        * 4 = 1   clock delay
-        * 5 = 5/4 clock delay
-        * 6 = 3/2 clock delay
+       /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+        * freqency and n_banks specified in board_specific_parameters table.
         */
-       popts->write_data_delay = 5;
+       ddr_freq = get_ddr_freq(0) / 1000000;
+       for (i = 0; i < num_params; i++) {
+               if (ddr_freq >= pbsp->datarate_mhz_low &&
+                   ddr_freq <= pbsp->datarate_mhz_high &&
+                   pdimm->n_ranks == pbsp->n_ranks) {
+                       popts->clk_adjust = pbsp->clk_adjust;
+                       popts->cpo_override = pbsp->cpo;
+                       popts->write_data_delay = pbsp->write_data_delay;
+                       popts->twoT_en = pbsp->force_2T;
+               }
+               pbsp++;
+       }
 
        /*
         * Factors to consider for half-strength driver enable:

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c2ed961cfd7d392de60f63295e8cc1d35557da4a..c2606fa03c12a04fadad33e1b59e52ecdeec06d5 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -61,7 +61,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ    get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ    get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ        33333333  /* ICS307 clock chip ref freq */
+#define CONFIG_ICS307_REFCLK_HZ        33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307       /* decode sysclk and ddrclk freq
                                             from ICS307 instead of switches */
 
@@ -549,6 +549,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_BAUDRATE        115200
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
+ "memctl_intlv_ctl=2\0"                                                \
  "netdev=eth0\0"                                               \
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                                \
  "tftpflash=tftpboot $loadaddr $uboot; "                       \