IB/mlx5: Fix cached MR allocation flow

When we have a miss in one order of the mkey cache, we try to get
an mkey from a higher order.

We still need to check that the higher order can be used with UMR
before using it. Otherwise, we will get an mkey with 0 entries and
the post send operation that is used to fill it will complete with
the following error:

mlx5_0:dump_cqe:275:(pid 0): dump error cqe
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 0f007806 25000025 49ce59d2

Fixes: 49780d42dfc9 ("IB/mlx5: Expose MR cache for mlx5_ib")
Cc: <stable@vger.kernel.org> # v4.10+
Signed-off-by: Majd Dibbiny <majd@mellanox.com>
Reviewed-by: Ilya Lesokhin <ilyal@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>

diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 2c40a2e989d26bfbe9449d0beb3763a49fa81cf7..a0eb2f96179a952e24d01238afa0e40497ce7257 100644 (file)
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -48,6 +48,7 @@ enum {
 #define MLX5_UMR_ALIGN 2048
 
 static int clean_mr(struct mlx5_ib_mr *mr);
+static int max_umr_order(struct mlx5_ib_dev *dev);
 static int use_umr(struct mlx5_ib_dev *dev, int order);
 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
 
@@ -491,16 +492,18 @@ static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
        struct mlx5_mr_cache *cache = &dev->cache;
        struct mlx5_ib_mr *mr = NULL;
        struct mlx5_cache_ent *ent;
+       int last_umr_cache_entry;
        int c;
        int i;
 
        c = order2idx(dev, order);
-       if (c < 0 || c > MAX_UMR_CACHE_ENTRY) {
+       last_umr_cache_entry = order2idx(dev, max_umr_order(dev));
+       if (c < 0 || c > last_umr_cache_entry) {
                mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
                return NULL;
        }
 
-       for (i = c; i < MAX_UMR_CACHE_ENTRY; i++) {
+       for (i = c; i <= last_umr_cache_entry; i++) {
                ent = &cache->ent[i];
 
                mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
@@ -816,11 +819,16 @@ static int get_octo_len(u64 addr, u64 len, int page_size)
        return (npages + 1) / 2;
 }
 
-static int use_umr(struct mlx5_ib_dev *dev, int order)
+static int max_umr_order(struct mlx5_ib_dev *dev)
 {
        if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
-               return order <= MAX_UMR_CACHE_ENTRY + 2;
-       return order <= MLX5_MAX_UMR_SHIFT;
+               return MAX_UMR_CACHE_ENTRY + 2;
+       return MLX5_MAX_UMR_SHIFT;
+}
+
+static int use_umr(struct mlx5_ib_dev *dev, int order)
+{
+       return order <= max_umr_order(dev);
 }
 
 static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length,