--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
+ model = "INABA Abaniact AML2-17GP";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs2_cfg";
+ reg = <0xa0000 0x400000>;
+ read-only;
+ };
+
+ partition@4a0000 {
+ label = "jffs2_log";
+ reg = <0x4a0000 0x100000>;
+ read-only;
+ };
+
+ partition@5a0000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x5a0000 0xd30000>;
+ openwrt,ih-magic = <0x83800000>;
+ };
+
+ partition@12d0000 {
+ label = "runtime2";
+ reg = <0x12d0000 0xd30000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+
+ port@24 {
+ reg = <24>;
+ label = "wan";
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};