am33xx: Add support, update omap3 McSPI driver

Signed-off-by: Tom Rini <trini@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 1071f925cc171c76c8f6d972d64bf6b4fed89510..2b19506a341c01a39a5347aba4a76f865829689e 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -148,6 +148,11 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
        while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
                ;
+
+       /* spi0 */
+       writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+       while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 static void mpu_pll_config(void)

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 9346c0b5b4af679d3015af0bbb35b78eecbc005d..47f9e56f421e27fdc933951db8ebf29ac3699fcb 100644 (file)
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -86,15 +86,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
        case 0:
                ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
                break;
+#ifdef OMAP3_MCSPI2_BASE
        case 1:
                ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
                break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE 
        case 2:
                ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
                break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
        case 3:
                ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
                break;
+#endif
        default:
                printf("SPI error: unsupported bus %i. \
                        Supported busses 0 - 3\n", bus);

diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 0ac801cb251f68e9a382d1b088b099a38c2d466d..bffa43cb6c7b26a8fc28501e8efa037ca93d42aa 100644 (file)
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -30,10 +30,15 @@
 #ifndef _OMAP3_SPI_H_
 #define _OMAP3_SPI_H_
 
+#ifdef CONFIG_AM33XX
+#define OMAP3_MCSPI1_BASE      0x48030100
+#define OMAP3_MCSPI2_BASE      0x481A0100
+#else
 #define OMAP3_MCSPI1_BASE      0x48098000
 #define OMAP3_MCSPI2_BASE      0x4809A000
 #define OMAP3_MCSPI3_BASE      0x480B8000
 #define OMAP3_MCSPI4_BASE      0x480BA000
+#endif
 
 #define OMAP3_MCSPI_MAX_FREQ   48000000