Adapt and refresh patches to apply.
DSA and ethernet driver patches are dropped as they will be replaced with
the latest version that was sent upstream.
Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
-@@ -624,6 +624,41 @@ not_relocated: mov r0, #0
+@@ -620,6 +620,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2447,7 +2447,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
+@@ -2451,7 +2451,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
-@@ -389,6 +389,29 @@ int qcom_scm_set_remote_state(u32 state,
+@@ -400,6 +400,29 @@ int qcom_scm_set_remote_state(u32 state,
}
EXPORT_SYMBOL(qcom_scm_set_remote_state);
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
+ #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
- #define QCOM_SCM_FLUSH_FLAG_MASK 0x3
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
-@@ -1337,6 +1337,13 @@ static int qcom_scm_probe(struct platfor
+@@ -1435,6 +1435,13 @@ static int qcom_scm_probe(struct platfor
if (download_mode)
qcom_scm_set_download_mode(true);
/**
* scm_legacy_call() - Sends a command to the SCM and waits for the command to
* finish processing.
-@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,
+@@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
rsp = scm_legacy_command_to_response(cmd);
}
smc.args[0] = 1;
-@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,
+@@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
goto out;
do {
if (res) {
res_buf = scm_legacy_get_response_buffer(rsp);
-@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,
+@@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
res->result[i] = le32_to_cpu(res_buf[i]);
}
out:
}
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
-@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en
+@@ -305,6 +305,17 @@ static int qcom_scm_set_boot_addr(void *
desc.args[0] = flags;
desc.args[1] = virt_to_phys(entry);
+
return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
- EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
+
+++ /dev/null
-From da75807ac41175e9db8c95f7a172b4133763b744 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Mon, 11 Jan 2021 17:49:36 +0100
-Subject: [PATCH] skbuff: add DSA specific data to struct skb_shared_info
-
-All of the already existing DSA tagging protocol drivers
-are storing the tagging data directly into the skb. In most
-cases that is the only way to send the required information
-to the underlying ethernet switch.
-
-However on certain platforms (like the Qualcomm IPQ40xx
-SoCs) the built-in ethernet switch is connected directly
-to an ethernet MAC, and the tagging information must be
-sent out-of-band which is done directly via the hardware
-TX descriptors of the ethernet MAC.
-
-In such cases, putting the information into the skb causes
-unneccesary overhead, because the ethernet driver must
-remove that before sending the ethernet frame towards to
-the hardware.
-
-This change adds two new DSA specific fields to struct
-skb_shared_info which makes it possible to send the
-tagging information via skb->shinfo. With this approach,
-the twofold modifications of the skb data can be avoided.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- include/linux/skbuff.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -564,6 +564,9 @@ struct skb_shared_info {
- unsigned int gso_type;
- u32 tskey;
-
-+ unsigned int dsa_tag_proto;
-+ unsigned char dsa_tag_data[8];
-+
- /*
- * Warning : all fields before dataref are cleared in __alloc_skb()
- */
+++ /dev/null
-From 29a0c2fae991cab142575c92276c0afdeb260ebe Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Thu, 28 Oct 2021 21:44:52 +0200
-Subject: [PATCH] net: dsa: tag_ipq4019: add shinfo based tagging driver for
- IPQ40xx
-
-This change adds a tagging protocol driver for the built-in
-ethernet switch of the Qualcomm Atheros IPQ4019 SoCs.
-
-In comparison to the existing tagging protocols this hardware
-requires a slightly different approach because the switch does
-not use in-band tags.
-
-On the receive path, the source port information is embedded
-into the RX descriptors of the ethernet MAC hardware. Similarly,
-the destination port mask must be sent via the TX descriptors
-of the ethernet MAC when a packet is sent towards the switch.
-
-In order to support this special requirements, this patch
-adds a new tagging protocol driver.
-
-The driver extracts the source port information directly
-from the 'receive return descriptor' of the ethernet MAC.
-It is possible because that descriptor is part of the skb
-received from the ethernet driver.
-
-Unfortunatley, it is not possible to put the destination
-port information directly to the TX descriptors, because
-those are handled internally by the driver of the ethernet
-hardware.
-
-To overcome this limitation, this tagging driver uses the
-DSA specific fields in skb->shinfo to send the destination
-port information to the ethernet driver.
-
-A similar tagging driver is exist but that uses skb
-extensions which causes unnecessary overhead.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- include/linux/dsa/ipq4019.h | 11 ++++++
- include/net/dsa.h | 2 +
- net/dsa/Kconfig | 6 +++
- net/dsa/Makefile | 1 +
- net/dsa/tag_ipq4019.c | 79 +++++++++++++++++++++++++++++++++++++
- 5 files changed, 99 insertions(+)
- create mode 100644 include/linux/dsa/ipq4019.h
- create mode 100644 net/dsa/tag_ipq4019.c
-
---- /dev/null
-+++ b/include/linux/dsa/ipq4019.h
-@@ -0,0 +1,11 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef DSA_IPQ40XX_H
-+#define DSA_IPQ40XX_H
-+
-+struct ipq40xx_dsa_tag_data {
-+ u8 from_cpu;
-+ u8 dp;
-+};
-+
-+#endif /* DSA_IPQ40XX_H */
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -51,6 +51,7 @@ struct phylink_link_state;
- #define DSA_TAG_PROTO_SEVILLE_VALUE 21
- #define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22
- #define DSA_TAG_PROTO_SJA1110_VALUE 23
-+#define DSA_TAG_PROTO_IPQ4019_VALUE 24
-
- enum dsa_tag_protocol {
- DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
-@@ -77,6 +78,7 @@ enum dsa_tag_protocol {
- DSA_TAG_PROTO_OCELOT_8021Q = DSA_TAG_PROTO_OCELOT_8021Q_VALUE,
- DSA_TAG_PROTO_SEVILLE = DSA_TAG_PROTO_SEVILLE_VALUE,
- DSA_TAG_PROTO_SJA1110 = DSA_TAG_PROTO_SJA1110_VALUE,
-+ DSA_TAG_PROTO_IPQ4019 = DSA_TAG_PROTO_IPQ4019_VALUE,
- };
-
- struct dsa_switch;
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -57,6 +57,12 @@ config NET_DSA_TAG_HELLCREEK
- Say Y or M if you want to enable support for tagging frames
- for the Hirschmann Hellcreek TSN switches.
-
-+config NET_DSA_TAG_IPQ4019
-+ tristate "Tag driver for Qualcomm Atheros IPQ4019 SoC built-in switch"
-+ help
-+ Say Y or M if you want to enable support for tagging frames for
-+ the built-in switch of the Qualcomm Atheros IPQ4019 SoC-s.
-+
- config NET_DSA_TAG_GSWIP
- tristate "Tag driver for Lantiq / Intel GSWIP switches"
- help
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_NET_DSA_TAG_AR9331) += tag_
- obj-$(CONFIG_NET_DSA_TAG_BRCM_COMMON) += tag_brcm.o
- obj-$(CONFIG_NET_DSA_TAG_DSA_COMMON) += tag_dsa.o
- obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o
-+obj-$(CONFIG_NET_DSA_TAG_IPQ4019) += tag_ipq4019.o
- obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o
- obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
- obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
---- /dev/null
-+++ b/net/dsa/tag_ipq4019.c
-@@ -0,0 +1,78 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+/* Copyright (c) 2021, Gabor Juhos <j4g8y7@gmail.com> */
-+
-+#include <linux/bitfield.h>
-+#include <linux/dsa/ipq4019.h>
-+
-+#include "dsa_priv.h"
-+
-+/* Receive Return Descriptor */
-+struct edma_rrd {
-+ u16 rrd0;
-+ u16 rrd1;
-+ u16 rrd2;
-+ u16 rrd3;
-+ u16 rrd4;
-+ u16 rrd5;
-+ u16 rrd6;
-+ u16 rrd7;
-+} __packed;
-+
-+#define EDMA_RRD_SIZE sizeof(struct edma_rrd)
-+
-+#define EDMA_RRD1_PORT_ID_MASK GENMASK(14, 12)
-+
-+static struct sk_buff *ipq4019_sh_tag_xmit(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_port *dp = dsa_slave_to_port(dev);
-+ struct ipq40xx_dsa_tag_data *tag_data;
-+
-+ BUILD_BUG_ON(sizeof_field(struct skb_shared_info, dsa_tag_data) <
-+ sizeof(struct ipq40xx_dsa_tag_data));
-+
-+ skb_shinfo(skb)->dsa_tag_proto = DSA_TAG_PROTO_IPQ4019;
-+ tag_data = (struct ipq40xx_dsa_tag_data *)skb_shinfo(skb)->dsa_tag_data;
-+
-+ tag_data->from_cpu = 1;
-+ /* set the destination port information */
-+ tag_data->dp = BIT(dp->index);
-+
-+ return skb;
-+}
-+
-+static struct sk_buff *ipq4019_sh_tag_rcv(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct edma_rrd *rrd;
-+ int offset;
-+ int port;
-+
-+ offset = EDMA_RRD_SIZE + ETH_HLEN;
-+ if (unlikely(skb_headroom(skb) < offset))
-+ return NULL;
-+
-+ rrd = (struct edma_rrd *)(skb->data - offset);
-+ port = FIELD_GET(EDMA_RRD1_PORT_ID_MASK, rrd->rrd1);
-+
-+ skb->dev = dsa_master_find_slave(dev, 0, port);
-+ if (!skb->dev)
-+ return NULL;
-+
-+ return skb;
-+}
-+
-+const struct dsa_device_ops ipq4019_sh_tag_dsa_ops = {
-+ .name = "ipq4019-sh",
-+ .proto = DSA_TAG_PROTO_IPQ4019,
-+ .xmit = ipq4019_sh_tag_xmit,
-+ .rcv = ipq4019_sh_tag_rcv,
-+};
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("DSA tag driver for the IPQ4019 SoC built-in ethernet switch");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
-+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_IPQ4019);
-+
-+module_dsa_tag_driver(ipq4019_sh_tag_dsa_ops);
+++ /dev/null
-From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 12:36:51 +0100
-Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
-
-Allow compiling the IPQESS driver that supports the
-Qualcomm IPQ40xx SoC built-in ethernet controller.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
- drivers/net/ethernet/qualcomm/Makefile | 1 +
- 2 files changed, 12 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -60,6 +60,17 @@ config QCOM_EMAC
- low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- Precision Clock Synchronization Protocol.
-
-+config QCOM_IPQ4019_ESS_EDMA
-+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
-+ depends on OF
-+ select PHYLINK
-+ help
-+ This driver supports the Qualcomm Atheros IPQ40xx built-in
-+ ESS EDMA ethernet controller.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called ipqess.
-+
- source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
-
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
- qcauart-objs := qca_uart.o
-
- obj-y += emac/
-+obj-y += ipqess/
-
- obj-$(CONFIG_RMNET) += rmnet/
+++ /dev/null
-From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Fri, 25 Dec 2020 08:02:47 +0100
-Subject: [PATCH] net: phy: define PSGMII PHY interface mode
-
-The PSGMII interface is similar to QSGMII. The main difference
-is that the PSGMII interface combines five SGMII lines into a
-single link while in QSGMII only four lines are combined.
-
-Similarly to the QSGMII, this interface mode might also needs
-special handling within the MAC driver.
-
-Add definitions for the PHY layer to allow to express this type
-of connection between the MAC and PHY.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
- drivers/net/phy/phylink.c | 2 ++
- include/linux/phy.h | 3 +++
- 3 files changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-@@ -64,6 +64,7 @@ properties:
- - mii
- - gmii
- - sgmii
-+ - psgmii
- - qsgmii
- - tbi
- - rev-mii
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -366,6 +366,7 @@ void phylink_get_linkmodes(unsigned long
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
-+ case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_GMII:
-@@ -629,6 +630,7 @@ static int phylink_parse_mode(struct phy
-
- switch (pl->link_config.interface) {
- case PHY_INTERFACE_MODE_SGMII:
-+ case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- phylink_set(pl->supported, 10baseT_Half);
- phylink_set(pl->supported, 10baseT_Full);
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -139,6 +139,7 @@ typedef enum {
- PHY_INTERFACE_MODE_XGMII,
- PHY_INTERFACE_MODE_XLGMII,
- PHY_INTERFACE_MODE_MOCA,
-+ PHY_INTERFACE_MODE_PSGMII,
- PHY_INTERFACE_MODE_QSGMII,
- PHY_INTERFACE_MODE_TRGMII,
- PHY_INTERFACE_MODE_100BASEX,
-@@ -244,6 +245,8 @@ static inline const char *phy_modes(phy_
- return "xlgmii";
- case PHY_INTERFACE_MODE_MOCA:
- return "moca";
-+ case PHY_INTERFACE_MODE_PSGMII:
-+ return "psgmii";
- case PHY_INTERFACE_MODE_QSGMII:
- return "qsgmii";
- case PHY_INTERFACE_MODE_TRGMII:
+++ /dev/null
-From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:10:28 +0100
-Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support
-
-Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
-
-It shares most of the stuff with its external counterpart, however it is
-modified for the SoC.
-Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
-instead of 7.
-It also has no built-in PHY-s but rather requires external PSGMII based
-companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
-out calibration before using them.
-PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
-unfortunately requires some magic values as the datasheet doesnt document
-the bits that are being set or the register at all.
-
-Since its built-in it is MMIO like other peripherals and doesn't have its
-own MDIO bus but depends on the SoC provided one.
-
-CPU connection is at Port 0 and it uses some kind of a internal connection
-and no traditional RGMII/SGMII.
-It also doesn't use in-band tagging like other qca8k switches so a shinfo
-based tagger is used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/dsa/qca/Kconfig | 9 +++++++++
- drivers/net/dsa/qca/Makefile | 1 +
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/dsa/qca/Kconfig
-+++ b/drivers/net/dsa/qca/Kconfig
-@@ -23,3 +23,13 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
- help
- This enabled support for LEDs present on the Qualcomm Atheros
- QCA8K Ethernet switch chips.
-+
-+config NET_DSA_QCA8K_IPQ4019
-+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support"
-+ depends on HAS_IOMEM && NET_DSA
-+ select NET_DSA_TAG_IPQ4019
-+ select REGMAP
-+ help
-+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in
-+ Ethernet switch.
-+
---- a/drivers/net/dsa/qca/Makefile
-+++ b/drivers/net/dsa/qca/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
-+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o
- obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
- qca8k-y += qca8k-common.o qca8k-8xxx.o
- ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT
-From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
+From 8cbdb2526c3d7ba2e0c8c771773595f195135f54 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 18:15:04 +0100
Subject: [PATCH] arm: dts: ipq4019: add switch node
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
- 1 file changed, 78 insertions(+)
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 76 +++++++++++++++++++++++++++++
+ 1 file changed, 76 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -590,6 +590,82 @@
+@@ -591,6 +591,82 @@
status = "disabled";
};
-From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
+From dfba344da3657ee4d91e7ebd1217e93423d03624 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
-From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
+From 95179775debad6b0bdab241d4a305135fc5e67dc Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
-Date: Wed, 7 Oct 2020 17:38:48 +0200
+Date: Fri, 9 Sep 2022 23:44:42 +0200
Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
- drivers/net/phy/Kconfig | 6 ++++++
+ drivers/net/phy/Kconfig | 7 +++++++
drivers/net/phy/Makefile | 1 +
- 2 files changed, 7 insertions(+)
+ 2 files changed, 8 insertions(+)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -347,6 +347,12 @@ config AT803X_PHY
+@@ -362,6 +362,13 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
+config QCA807X_PHY
-+ tristate "Qualcomm QCA807X PHYs"
++ tristate "Qualcomm QCA807x PHYs"
+ depends on OF_MDIO
+ help
-+ Currently supports the QCA8072 and QCA8075 models.
++ Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII
++ control PHY.
+
config QSEMI_PHY
tristate "Quality Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -92,6 +92,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
+@@ -94,6 +94,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm
+ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
- obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
+ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
-From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
+From 03ebcd291974e4ca5d77026111f63309bc708326 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 2 Oct 2020 10:43:26 +0200
Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
/ {
#address-cells = <1>;
-@@ -726,22 +727,38 @@
+@@ -724,22 +725,38 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
- obj-$(CONFIG_QCOM_SMSM) += smsm.o
- obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
-@@ -192,6 +192,13 @@ config QCOM_SOCINFO
- Say yes here to support the Qualcomm socinfo driver, providing
- information about the SoC to user space.
+@@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
+ the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
+ memory throughput even with lower CPU frequencies.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
- config QCOM_WCNSS_CTRL
- tristate "Qualcomm WCNSS control driver"
- depends on ARCH_QCOM || COMPILE_TEST
+ endmenu
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
+ obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
+ obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
+ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
-@@ -1361,7 +1361,8 @@ static int qcom_scm_probe(struct platfor
+@@ -1459,7 +1459,8 @@ static int qcom_scm_probe(struct platfor
static void qcom_scm_shutdown(struct platform_device *pdev)
{
/* Clean shutdown, disable download mode to allow normal restart */
--- a/drivers/net/ppp/ppp_generic.c
+++ b/drivers/net/ppp/ppp_generic.c
-@@ -2952,6 +2952,22 @@ char *ppp_dev_name(struct ppp_channel *c
+@@ -2953,6 +2953,22 @@ char *ppp_dev_name(struct ppp_channel *c
return name;
}
/*
* Disconnect a channel from the generic layer.
-@@ -3598,6 +3614,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
+@@ -3599,6 +3615,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
EXPORT_SYMBOL(ppp_channel_index);
EXPORT_SYMBOL(ppp_unit_number);
EXPORT_SYMBOL(ppp_dev_name);
EXPORT_SYMBOL(ppp_output_wakeup);
--- a/include/linux/ppp_channel.h
+++ b/include/linux/ppp_channel.h
-@@ -74,6 +74,9 @@ extern int ppp_unit_number(struct ppp_ch
+@@ -76,6 +76,9 @@ extern int ppp_unit_number(struct ppp_ch
/* Get the device name associated with a channel, or NULL if none */
extern char *ppp_dev_name(struct ppp_channel *);
depends on ATM && INET
--- a/net/atm/br2684.c
+++ b/net/atm/br2684.c
-@@ -596,6 +596,11 @@ static int br2684_regvcc(struct atm_vcc
+@@ -598,6 +598,11 @@ static int br2684_regvcc(struct atm_vcc
atmvcc->push = br2684_push;
atmvcc->pop = br2684_pop;
atmvcc->release_cb = br2684_release_cb;
projects / openwrt / staging / dangole.git / commitdiff