ls102x: configs - Add hash command in freescale LS1 platforms
authorRuchika Gupta <ruchika.gupta@freescale.com>
Wed, 15 Oct 2014 06:09:06 +0000 (11:39 +0530)
committerYork Sun <yorksun@freescale.com>
Thu, 16 Oct 2014 21:17:32 +0000 (14:17 -0700)
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/include/asm/arch-ls102xa/config.h
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1021atwr/ls1021atwr.c
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h

index a500b5bc3b6581b9e72a73998d8ee3ded1d55034..f2c9687df42cb9da9cc480cc0d35b5255a400c9e 100644 (file)
@@ -19,6 +19,8 @@
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_SCFG_ADDR               (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_SEC_ADDR                        (CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR                        (CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_FSL_SERDES_ADDR             (CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR            (CONFIG_SYS_IMMR + 0x00ee1000)
@@ -66,6 +68,7 @@
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_LE
 
 #define DCU_LAYER_MAX_NUM                      16
 
@@ -76,6 +79,7 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1
 #define CONFIG_SYS_FSL_DDR_VER                 FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_SEC_COMPAT              5
 #else
 #error SoC not defined
 #endif
index 12e83f764546e5ae5b372de84b569036c9373079..5fafc8567207d3d777f40567dfb90aec92670196 100644 (file)
@@ -13,6 +13,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <fsl_sec.h>
 
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -213,6 +214,15 @@ int config_serdes_mux(void)
        return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_CAAM
+       return sec_init();
+#endif
+}
+#endif
+
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
index b522ff28e5eb8e7c87ffd6c10430beaa5798669b..50d564055b173ddd2ee46db63b2797168e7e2544 100644 (file)
@@ -16,6 +16,7 @@
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,15 @@ int board_init(void)
        return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_CAAM
+       return sec_init();
+#endif
+}
+#endif
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
index bb4781334537b579bc07b52ab76cba69f79b5ea6..139583fea1fd3ac0b6f7e7f49b87c1671a6addc9 100644 (file)
@@ -69,6 +69,7 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_HAS_SERDES
 
+#define CONFIG_FSL_CAAM                        /* Enable CAAM */
 /*
  * IFC Definitions
  */
@@ -388,4 +389,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
 #endif
index 45b2272ff5bf6f7f390ee6935bc5908b402369eb..ebe5daef60b405facb7215612c3425fb51c80ace 100644 (file)
@@ -48,6 +48,8 @@
 
 #define CONFIG_SYS_HAS_SERDES
 
+#define CONFIG_FSL_CAAM                        /* Enable CAAM */
+
 /*
  * IFC Definitions
  */
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
 #endif