* @freq_msg: tuning word spi message
* @phase_xfer: tuning word spi transfer
* @phase_msg: tuning word spi message
+ * @lock protect sensor state
* @data: spi transmit buffer
* @phase_data: tuning word spi transmit buffer
* @freq_data: tuning word spi transmit buffer
struct spi_message freq_msg;
struct spi_transfer phase_xfer[2];
struct spi_message phase_msg;
+ struct mutex lock; /* protect sensor state */
/*
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
if (ret)
goto error_ret;
- mutex_lock(&indio_dev->mlock);
+ mutex_lock(&st->lock);
switch ((u32)this_attr->address) {
case AD9832_FREQ0HM:
case AD9832_FREQ1HM:
default:
ret = -ENODEV;
}
- mutex_unlock(&indio_dev->mlock);
+ mutex_unlock(&st->lock);
error_ret:
return ret ? ret : len;
st->mclk = pdata->mclk;
st->spi = spi;
+ mutex_init(&st->lock);
indio_dev->dev.parent = &spi->dev;
indio_dev->name = spi_get_device_id(spi)->name;