dt-binding: spi: add NPCM PSPI controller documentation

Added device tree binding documentation for Nuvoton BMC
NPCM Peripheral SPI controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
new file mode 100644 (file)
index 0000000..99606b2
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+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
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+Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
+
+Nuvoton NPCM7xx SOC support two PSPI channels.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
+ - #address-cells : should be 1. see spi-bus.txt
+ - #size-cells : should be 0. see spi-bus.txt
+ - specifies physical base address and size of the register.
+ - interrupts : contain PSPI interrupt.
+ - clocks : phandle of PSPI reference clock.
+ - clock-names: Should be "clk_apb5".
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+ - cs-gpios: Specifies the gpio pins to be used for chipselects.
+            See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- clock-frequency : Input clock frequency to the PSPI block in Hz.
+                   Default is 25000000 Hz.
+
+Example:
+
+spi0: spi@f0200000 {
+       compatible = "nuvoton,npcm750-pspi";
+       reg = <0xf0200000 0x1000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pspi1_pins>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+       clocks = <&clk NPCM7XX_CLK_APB5>;
+       clock-names = "clk_apb5";
+       cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+};