# CONFIG_B53_SRAB_DRIVER is not set
CONFIG_BCM63XX=y
CONFIG_BCM63XX_CPU_3368=y
+# CONFIG_BCM63XX_CPU_6318 is not set
# CONFIG_BCM63XX_CPU_63268 is not set
CONFIG_BCM63XX_CPU_6328=y
CONFIG_BCM63XX_CPU_6338=y
--- /dev/null
+From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 01:24:09 +0100
+Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
+
+---
+ arch/mips/bcm63xx/Kconfig | 5 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
+ arch/mips/bcm63xx/clk.c | 8 +-
+ arch/mips/bcm63xx/cpu.c | 53 +++++++++++
+ arch/mips/bcm63xx/dev-flash.c | 3 +
+ arch/mips/bcm63xx/dev-spi.c | 2 +-
+ arch/mips/bcm63xx/irq.c | 10 ++
+ arch/mips/bcm63xx/prom.c | 2 +-
+ arch/mips/bcm63xx/reset.c | 24 +++++
+ arch/mips/bcm63xx/setup.c | 5 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++-
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
+ 13 files changed, 291 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -18,6 +18,11 @@ config BCM63XX_EHCI
+ select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
+ select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
+
++config BCM63XX_CPU_6318
++ bool "support 6318 CPU"
++ select SYS_HAS_CPU_BMIPS32_3300
++ select HW_HAS_PCI
++
+ config BCM63XX_CPU_6328
+ bool "support 6328 CPU"
+ select SYS_HAS_CPU_BMIPS4350
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -825,7 +825,7 @@ void __init board_prom_init(void)
+ /* read base address of boot chip select (0)
+ * 6328/6362 do not have MPI but boot from a fixed address
+ */
+- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
+ val = 0x18000000;
+ } else {
+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -252,7 +252,9 @@ static void hsspi_set(struct clk *clk, i
+ {
+ u32 mask;
+
+- if (BCMCPU_IS_6328())
++ if (BCMCPU_IS_6318())
++ mask = CKCTL_6318_HSSPI_EN;
++ else if (BCMCPU_IS_6328())
+ mask = CKCTL_6328_HSSPI_EN;
+ else if (BCMCPU_IS_6362())
+ mask = CKCTL_6362_HSSPI_EN;
+@@ -405,12 +407,16 @@ void clk_put(struct clk *clk)
+
+ EXPORT_SYMBOL(clk_put);
+
++#define HSSPI_PLL_HZ_6318 250000000
+ #define HSSPI_PLL_HZ_6328 133333333
+ #define HSSPI_PLL_HZ_6362 400000000
+
+ static int __init bcm63xx_clk_init(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6318_CPU_ID:
++ clk_hsspi.rate = HSSPI_PLL_HZ_6318;
++ break;
+ case BCM6328_CPU_ID:
+ clk_hsspi.rate = HSSPI_PLL_HZ_6328;
+ break;
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = {
+ __GEN_CPU_IRQ_TABLE(3368)
+ };
+
++static const unsigned long bcm6318_regs_base[] = {
++ __GEN_CPU_REGS_TABLE(6318)
++};
++
++static const int bcm6318_irqs[] = {
++ __GEN_CPU_IRQ_TABLE(6318)
++};
++
+ static const unsigned long bcm6328_regs_base[] = {
+ __GEN_CPU_REGS_TABLE(6328)
+ };
+@@ -134,12 +142,38 @@ unsigned int bcm63xx_get_memory_size(voi
+ return bcm63xx_memory_size;
+ }
+
++#define STRAP_OVERRIDE_BUS_REG 0x0
++#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23
++#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT)
++
+ static unsigned int detect_cpu_clock(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
+ case BCM3368_CPU_ID:
+ return 300000000;
+
++ case BCM6318_CPU_ID:
++ {
++ unsigned int tmp, mips_pll_fcvo;
++
++ tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG);
++
++ pr_info("strap_override_bus = %08x\n", tmp);
++
++ mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK)
++ >> OVERRIDE_BUS_MIPS_FREQ_SHIFT;
++
++ switch (mips_pll_fcvo) {
++ case 0:
++ return 166000000;
++ case 1:
++ return 400000000;
++ case 2:
++ return 250000000;
++ case 3:
++ return 333000000;
++ };
++ }
+ case BCM6328_CPU_ID:
+ {
+ unsigned int tmp, mips_pll_fcvo;
+@@ -295,6 +329,13 @@ static unsigned int detect_memory_size(v
+ unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ u32 val;
+
++ if (BCMCPU_IS_6318()) {
++ val = bcm_sdram_readl(SDRAM_CFG_REG);
++ val = val & SDRAM_CFG_6318_SPACE_MASK;
++ val >>= SDRAM_CFG_6318_SPACE_SHIFT;
++ return 1 << (val + 20);
++ }
++
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
+ return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+
+@@ -342,6 +383,12 @@ void __init bcm63xx_cpu_init(void)
+
+ switch (c->cputype) {
+ case CPU_BMIPS3300:
++ if ((read_c0_prid() & 0xff) >= 0x33) {
++ /* BCM6318 */
++ chipid_reg = BCM_6368_PERF_BASE;
++ break;
++ }
++
+ if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
+ __cpu_name[cpu] = "Broadcom BCM6338";
+ /* fall-through */
+@@ -389,6 +436,10 @@ void __init bcm63xx_cpu_init(void)
+ bcm63xx_cpu_variant = bcm63xx_cpu_id;
+
+ switch (bcm63xx_cpu_id) {
++ case BCM6318_CPU_ID:
++ bcm63xx_regs_base = bcm6318_regs_base;
++ bcm63xx_irqs = bcm6318_irqs;
++ break;
+ case BCM3368_CPU_ID:
+ bcm63xx_regs_base = bcm3368_regs_base;
+ bcm63xx_irqs = bcm3368_irqs;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t
+ u32 val;
+
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6318_CPU_ID:
++ /* only support serial flash */
++ return BCM63XX_FLASH_TYPE_SERIAL;
+ case BCM6328_CPU_ID:
+ val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+ if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -70,7 +70,7 @@ static struct platform_device bcm63xx_sp
+
+ int __init bcm63xx_spi_register(void)
+ {
+- if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())
+ return -ENODEV;
+
+ spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -441,6 +441,16 @@ static void bcm63xx_init_irq(void)
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
+ break;
++ case BCM6318_CPU_ID:
++ irq_stat_addr[0] += PERF_IRQSTAT_6318_REG;
++ irq_mask_addr[0] += PERF_IRQMASK_6318_REG;
++ irq_bits = 128;
++ ext_irq_count = 4;
++ is_ext_irq_cascaded = 1;
++ ext_irq_start = BCM_6318_EXT_IRQ0 - IRQ_INTERNAL_BASE;
++ ext_irq_end = BCM_6318_EXT_IRQ3 - IRQ_INTERNAL_BASE;
++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6318;
++ break;
+ case BCM6328_CPU_ID:
+ irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
+ irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -72,7 +72,7 @@ void __init prom_init(void)
+
+ if (reg & OTP_6328_REG3_TP1_DISABLED)
+ bmips_smp_enabled = 0;
+- } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
++ } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
+ bmips_smp_enabled = 0;
+ }
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -43,6 +43,23 @@
+ #define BCM3368_RESET_PCIE 0
+ #define BCM3368_RESET_PCIE_EXT 0
+
++
++#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK
++#define BCM6318_RESET_ENET 0
++#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK
++#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK
++#define BCM6318_RESET_DSL 0
++#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK
++#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK
++#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK
++#define BCM6318_RESET_PCM 0
++#define BCM6318_RESET_MPI 0
++#define BCM6318_RESET_PCIE \
++ (SOFTRESET_6318_PCIE_MASK | \
++ SOFTRESET_6318_PCIE_CORE_MASK | \
++ SOFTRESET_6318_PCIE_HARD_MASK)
++#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
++
+ #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
+ #define BCM6328_RESET_ENET 0
+ #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
+@@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] =
+ __GEN_RESET_BITS_TABLE(3368)
+ };
+
++static const u32 bcm6318_reset_bits[] = {
++ __GEN_RESET_BITS_TABLE(6318)
++};
++
+ static const u32 bcm6328_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6328)
+ };
+@@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini
+ if (BCMCPU_IS_3368()) {
+ reset_reg = PERF_SOFTRESET_6358_REG;
+ bcm63xx_reset_bits = bcm3368_reset_bits;
++ } else if (BCMCPU_IS_6318()) {
++ reset_reg = PERF_SOFTRESET_6318_REG;
++ bcm63xx_reset_bits = bcm6318_reset_bits;
+ } else if (BCMCPU_IS_6328()) {
+ reset_reg = PERF_SOFTRESET_6328_REG;
+ bcm63xx_reset_bits = bcm6328_reset_bits;
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -71,6 +71,9 @@ void bcm63xx_machine_reboot(void)
+ case BCM3368_CPU_ID:
+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
+ break;
++ case BCM6318_CPU_ID:
++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318;
++ break;
+ case BCM6328_CPU_ID:
+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
+ break;
+@@ -110,7 +113,7 @@ void bcm63xx_machine_reboot(void)
+ bcm6348_a1_reboot();
+
+ printk(KERN_INFO "triggering watchdog soft-reset...\n");
+- if (BCMCPU_IS_6328()) {
++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) {
+ bcm_wdt_writel(1, WDT_SOFTRESET_REG);
+ } else {
+ reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -10,6 +10,7 @@
+ * arm mach-types)
+ */
+ #define BCM3368_CPU_ID 0x3368
++#define BCM6318_CPU_ID 0x6318
+ #define BCM6328_CPU_ID 0x6328
+ #define BCM63281_CPU_ID 0x63281
+ #define BCM63283_CPU_ID 0x63283
+@@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c
+ case BCM3368_CPU_ID:
+ #endif
+
++#ifdef CONFIG_BCM63XX_CPU_6318
++ case BCM6318_CPU_ID:
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ case BCM6328_CPU_ID:
+ #endif
+@@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu
+ }
+
+ #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
++#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID)
+ #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
+ #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+ #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+@@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu
+
+ #define BCMCPU_VARIANT_IS_3368() \
+ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
++#define BCMCPU_VARIANT_IS_6318() \
++ (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID)
+ #define BCMCPU_VARIANT_IS_63281() \
+ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
+ #define BCMCPU_VARIANT_IS_63283() \
+@@ -252,6 +260,56 @@ enum bcm63xx_regs_set {
+ #define BCM_3368_MISC_BASE (0xdeadbeef)
+
+ /*
++ * 6318 register sets base address
++ */
++#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef)
++#define BCM_6318_PERF_BASE (0xb0000000)
++#define BCM_6318_TIMER_BASE (0xb0000040)
++#define BCM_6318_WDT_BASE (0xb0000068)
++#define BCM_6318_UART0_BASE (0xb0000100)
++#define BCM_6318_UART1_BASE (0xdeadbeef)
++#define BCM_6318_GPIO_BASE (0xb0000080)
++#define BCM_6318_SPI_BASE (0xdeadbeef)
++#define BCM_6318_HSSPI_BASE (0xb0003000)
++#define BCM_6318_UDC0_BASE (0xdeadbeef)
++#define BCM_6318_USBDMA_BASE (0xdeadbeef)
++#define BCM_6318_OHCI0_BASE (0xb0005100)
++#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef)
++#define BCM_6318_USBH_PRIV_BASE (0xb0005200)
++#define BCM_6318_USBD_BASE (0xb0006000)
++#define BCM_6318_MPI_BASE (0xdeadbeef)
++#define BCM_6318_PCMCIA_BASE (0xdeadbeef)
++#define BCM_6318_PCIE_BASE (0xb0010000)
++#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef)
++#define BCM_6318_DSL_BASE (0xdeadbeef)
++#define BCM_6318_UBUS_BASE (0xdeadbeef)
++#define BCM_6318_ENET0_BASE (0xdeadbeef)
++#define BCM_6318_ENET1_BASE (0xdeadbeef)
++#define BCM_6318_ENETDMA_BASE (0xb0088000)
++#define BCM_6318_ENETDMAC_BASE (0xb0088200)
++#define BCM_6318_ENETDMAS_BASE (0xb0088400)
++#define BCM_6318_ENETSW_BASE (0xb0080000)
++#define BCM_6318_EHCI0_BASE (0xb0005000)
++#define BCM_6318_SDRAM_BASE (0xb0004000)
++#define BCM_6318_MEMC_BASE (0xdeadbeef)
++#define BCM_6318_DDR_BASE (0xdeadbeef)
++#define BCM_6318_M2M_BASE (0xdeadbeef)
++#define BCM_6318_ATM_BASE (0xdeadbeef)
++#define BCM_6318_XTM_BASE (0xdeadbeef)
++#define BCM_6318_XTMDMA_BASE (0xb000c000)
++#define BCM_6318_XTMDMAC_BASE (0xdeadbeef)
++#define BCM_6318_XTMDMAS_BASE (0xdeadbeef)
++#define BCM_6318_PCM_BASE (0xdeadbeef)
++#define BCM_6318_PCMDMA_BASE (0xdeadbeef)
++#define BCM_6318_PCMDMAC_BASE (0xdeadbeef)
++#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
++#define BCM_6318_RNG_BASE (0xdeadbeef)
++#define BCM_6318_MISC_BASE (0xb0000280)
++#define BCM_6318_OTP_BASE (0xdeadbeef)
++
++#define BCM_6318_STRAP_BASE (0xb0000900)
++
++/*
+ * 6328 register sets base address
+ */
+ #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
+@@ -819,6 +877,55 @@ enum bcm63xx_irq {
+ #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
+ #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
+
++/*
++ * 6318 irqs
++ */
++#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
++#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32)
++
++#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
++#define BCM_6318_SPI_IRQ 0
++#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
++#define BCM_6318_UART1_IRQ 0
++#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21)
++#define BCM_6318_UDC0_IRQ 0
++#define BCM_6318_ENET0_IRQ 0
++#define BCM_6318_ENET1_IRQ 0
++#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
++#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
++#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9)
++#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10)
++#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
++#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
++#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
++#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
++#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
++#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
++#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
++#define BCM_6318_PCMCIA_IRQ 0
++#define BCM_6318_ENET0_RXDMA_IRQ 0
++#define BCM_6318_ENET0_TXDMA_IRQ 0
++#define BCM_6318_ENET1_RXDMA_IRQ 0
++#define BCM_6318_ENET1_TXDMA_IRQ 0
++#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
++#define BCM_6318_ATM_IRQ 0
++#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0)
++#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1)
++#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2)
++#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3)
++#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10)
++#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11)
++#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12)
++#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13)
++#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31)
++#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11)
++
++#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
++#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
++#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
++#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
++#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
++#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
+
+ /*
+ * 6328 irqs
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -52,6 +52,39 @@
+ CKCTL_3368_EMUSB_EN | \
+ CKCTL_3368_USBU_EN)
+
++#define CKCTL_6318_ADSL_ASB_EN (1 << 0)
++#define CKCTL_6318_USB_ASB_EN (1 << 1)
++#define CKCTL_6318_MIPS_ASB_EN (1 << 2)
++#define CKCTL_6318_PCIE_ASB_EN (1 << 3)
++#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4)
++#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5)
++#define CKCTL_6318_SAR_ASB_EN (1 << 6)
++#define CKCTL_6318_SDR_ASB_EN (1 << 7)
++#define CKCTL_6318_SWREG_ASB_EN (1 << 8)
++#define CKCTL_6318_PERIPH_ASB_EN (1 << 9)
++#define CKCTL_6318_CPUBUS160_EN (1 << 10)
++#define CKCTL_6318_ADSL_EN (1 << 11)
++#define CKCTL_6318_SAR125_EN (1 << 12)
++#define CKCTL_6318_MIPS_EN (1 << 13)
++#define CKCTL_6318_PCIE_EN (1 << 14)
++#define CKCTL_6318_ROBOSW250_EN (1 << 16)
++#define CKCTL_6318_ROBOSW025_EN (1 << 17)
++#define CKCTL_6318_SDR_EN (1 << 19)
++#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */
++#define CKCTL_6318_HSSPI_EN (1 << 25)
++#define CKCTL_6318_PCIE25_EN (1 << 27)
++#define CKCTL_6318_PHYMIPS_EN (1 << 28)
++#define CKCTL_6318_ADSL_AFE_EN (1 << 29)
++#define CKCTL_6318_ADSL_QPROC_EN (1 << 30)
++
++#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \
++ CKCTL_6318_ADSL_QPROC_EN | \
++ CKCTL_6318_ADSL_AFE_EN | \
++ CKCTL_6318_ADSL_EN | \
++ CKCTL_6318_SAR_EN | \
++ CKCTL_6318_USB_EN | \
++ CKCTL_6318_PCIE_EN)
++
+ #define CKCTL_6328_PHYMIPS_EN (1 << 0)
+ #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
+ #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
+@@ -259,12 +292,27 @@
+ CKCTL_63268_TBUS_EN | \
+ CKCTL_63268_ROBOSW250_EN)
+
++/* UBUS Clock Control register */
++#define PERF_UB_CKCTL_REG 0x10
++
++#define UB_CKCTL_6318_ADSL_EN (1 << 0)
++#define UB_CKCTL_6318_ARB_EN (1 << 1)
++#define UB_CKCTL_6318_MIPS_EN (1 << 2)
++#define UB_CKCTL_6318_PCIE_EN (1 << 3)
++#define UB_CKCTL_6318_PERIPH_EN (1 << 4)
++#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5)
++#define UB_CKCTL_6318_ROBOSW_EN (1 << 6)
++#define UB_CKCTL_6318_SAR_EN (1 << 7)
++#define UB_CKCTL_6318_SDR_EN (1 << 8)
++#define UB_CKCTL_6318_USB_EN (1 << 9)
++
+ /* System PLL Control register */
+ #define PERF_SYS_PLL_CTL_REG 0x8
+ #define SYS_PLL_SOFT_RESET 0x1
+
+ /* Interrupt Mask register */
+ #define PERF_IRQMASK_3368_REG 0xc
++#define PERF_IRQMASK_6318_REG 0x20
+ #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
+ #define PERF_IRQMASK_6338_REG 0xc
+ #define PERF_IRQMASK_6345_REG 0xc
+@@ -276,6 +324,7 @@
+
+ /* Interrupt Status register */
+ #define PERF_IRQSTAT_3368_REG 0x10
++#define PERF_IRQSTAT_6318_REG 0x30
+ #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
+ #define PERF_IRQSTAT_6338_REG 0x10
+ #define PERF_IRQSTAT_6345_REG 0x10
+@@ -287,6 +336,7 @@
+
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_3368 0x14
++#define PERF_EXTIRQ_CFG_REG_6318 0x18
+ #define PERF_EXTIRQ_CFG_REG_6328 0x18
+ #define PERF_EXTIRQ_CFG_REG_6338 0x14
+ #define PERF_EXTIRQ_CFG_REG_6345 0x14
+@@ -320,6 +370,7 @@
+
+ /* Soft Reset register */
+ #define PERF_SOFTRESET_REG 0x28
++#define PERF_SOFTRESET_6318_REG 0x10
+ #define PERF_SOFTRESET_6328_REG 0x10
+ #define PERF_SOFTRESET_6358_REG 0x34
+ #define PERF_SOFTRESET_6362_REG 0x10
+@@ -333,6 +384,18 @@
+ #define SOFTRESET_3368_USBS_MASK (1 << 11)
+ #define SOFTRESET_3368_PCM_MASK (1 << 13)
+
++#define SOFTRESET_6318_SPI_MASK (1 << 0)
++#define SOFTRESET_6318_EPHY_MASK (1 << 1)
++#define SOFTRESET_6318_SAR_MASK (1 << 2)
++#define SOFTRESET_6318_ENETSW_MASK (1 << 3)
++#define SOFTRESET_6318_USBS_MASK (1 << 4)
++#define SOFTRESET_6318_USBH_MASK (1 << 5)
++#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6)
++#define SOFTRESET_6318_PCIE_MASK (1 << 7)
++#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8)
++#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9)
++#define SOFTRESET_6318_ADSL_MASK (1 << 10)
++
+ #define SOFTRESET_6328_SPI_MASK (1 << 0)
+ #define SOFTRESET_6328_EPHY_MASK (1 << 1)
+ #define SOFTRESET_6328_SAR_MASK (1 << 2)
+@@ -504,8 +567,17 @@
+ #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
+ #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
+
++#define TIMER_IRQMASK_6318_REG 0x0
++#define TIMER_IRQSTAT_6318_REG 0x4
++#define IRQSTATMASK_TIMER0 (1 << 0)
++#define IRQSTATMASK_TIMER1 (1 << 1)
++#define IRQSTATMASK_TIMER2 (1 << 2)
++#define IRQSTATMASK_TIMER3 (1 << 3)
++#define IRQSTATMASK_WDT (1 << 4)
++
+ /* Timer control register */
+ #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
++#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4))
+ #define TIMER_CTL0_REG 0x4
+ #define TIMER_CTL1_REG 0x8
+ #define TIMER_CTL2_REG 0xC
+@@ -1372,6 +1444,8 @@
+ #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
+ #define SDRAM_CFG_BANK_SHIFT 13
+ #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
++#define SDRAM_CFG_6318_SPACE_SHIFT 4
++#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT)
+
+ #define SDRAM_MBASE_REG 0xc
+
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re
+ if (offset >= 0xfff00000)
+ return 1;
+ break;
++ case BCM6318_CPU_ID:
+ case BCM6328_CPU_ID:
+ case BCM6362_CPU_ID:
+ case BCM6368_CPU_ID:
--- /dev/null
+From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 14:17:50 +0100
+Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals
+
+---
+ arch/mips/bcm63xx/reset.c | 39 ++++++++++++++--------
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++
+ arch/mips/pci/pci-bcm63xx.c | 7 ++++
+ 3 files changed, 34 insertions(+), 14 deletions(-)
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -28,7 +28,9 @@
+ [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
+ [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
+ [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
+- [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
++ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \
++ [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \
++ [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD,
+
+ #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
+ #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
+@@ -42,6 +44,8 @@
+ #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
+ #define BCM3368_RESET_PCIE 0
+ #define BCM3368_RESET_PCIE_EXT 0
++#define BCM3368_RESET_PCIE_CORE 0
++#define BCM3368_RESET_PCIE_HARD 0
+
+
+ #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK
+@@ -54,11 +58,10 @@
+ #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK
+ #define BCM6318_RESET_PCM 0
+ #define BCM6318_RESET_MPI 0
+-#define BCM6318_RESET_PCIE \
+- (SOFTRESET_6318_PCIE_MASK | \
+- SOFTRESET_6318_PCIE_CORE_MASK | \
+- SOFTRESET_6318_PCIE_HARD_MASK)
++#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK
+ #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
++#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK
++#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK
+
+ #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
+ #define BCM6328_RESET_ENET 0
+@@ -70,11 +73,10 @@
+ #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
+ #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
+ #define BCM6328_RESET_MPI 0
+-#define BCM6328_RESET_PCIE \
+- (SOFTRESET_6328_PCIE_MASK | \
+- SOFTRESET_6328_PCIE_CORE_MASK | \
+- SOFTRESET_6328_PCIE_HARD_MASK)
++#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK
+ #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
++#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK
++#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK
+
+ #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
+ #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
+@@ -88,6 +90,8 @@
+ #define BCM6338_RESET_MPI 0
+ #define BCM6338_RESET_PCIE 0
+ #define BCM6338_RESET_PCIE_EXT 0
++#define BCM6338_RESET_PCIE_CORE 0
++#define BCM6338_RESET_PCIE_HARD 0
+
+ #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
+ #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
+@@ -101,6 +105,8 @@
+ #define BCM6348_RESET_MPI 0
+ #define BCM6348_RESET_PCIE 0
+ #define BCM6348_RESET_PCIE_EXT 0
++#define BCM6348_RESET_PCIE_CORE 0
++#define BCM6348_RESET_PCIE_HARD 0
+
+ #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
+ #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
+@@ -114,6 +120,8 @@
+ #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
+ #define BCM6358_RESET_PCIE 0
+ #define BCM6358_RESET_PCIE_EXT 0
++#define BCM6358_RESET_PCIE_CORE 0
++#define BCM6358_RESET_PCIE_HARD 0
+
+ #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
+ #define BCM6362_RESET_ENET 0
+@@ -125,9 +133,10 @@
+ #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
+ #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
+ #define BCM6362_RESET_MPI 0
+-#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
+- SOFTRESET_6362_PCIE_CORE_MASK)
++#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK
+ #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
++#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK
++#define BCM6362_RESET_PCIE_HARD 0
+
+ #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
+ #define BCM6368_RESET_ENET 0
+@@ -141,6 +150,8 @@
+ #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
+ #define BCM6368_RESET_PCIE 0
+ #define BCM6368_RESET_PCIE_EXT 0
++#define BCM6368_RESET_PCIE_CORE 0
++#define BCM6368_RESET_PCIE_HARD 0
+
+ #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
+ #define BCM63268_RESET_ENET 0
+@@ -152,10 +163,10 @@
+ #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
+ #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
+ #define BCM63268_RESET_MPI 0
+-#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
+- SOFTRESET_63268_PCIE_CORE_MASK | \
+- SOFTRESET_63268_PCIE_HARD_MASK)
++#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK
+ #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
++#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK
++#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK
+
+ /*
+ * core reset bits
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
+@@ -14,6 +14,8 @@ enum bcm63xx_core_reset {
+ BCM63XX_RESET_MPI,
+ BCM63XX_RESET_PCIE,
+ BCM63XX_RESET_PCIE_EXT,
++ BCM63XX_RESET_PCIE_CORE,
++ BCM63XX_RESET_PCIE_HARD,
+ };
+
+ void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo
+
+ /* reset the PCIe core */
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
++ if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) {
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1);
++ mdelay(10);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
++ }
+ mdelay(10);
+
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
+ mdelay(10);
+
--- /dev/null
+From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 15 Dec 2013 20:47:34 +0100
+Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318
+
+---
+ arch/mips/bcm63xx/clk.c | 25 ++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 60 +++++++++++-
+ arch/mips/pci/ops-bcm63xx.c | 16 +++-
+ arch/mips/pci/pci-bcm63xx.c | 106 ++++++++++++++++++----
+ 5 files changed, 184 insertions(+), 29 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -50,6 +50,18 @@ static void bcm_hwclock_set(u32 mask, in
+ bcm_perf_writel(reg, PERF_CKCTL_REG);
+ }
+
++static void bcm_ub_hwclock_set(u32 mask, int enable)
++{
++ u32 reg;
++
++ reg = bcm_perf_readl(PERF_UB_CKCTL_REG);
++ if (enable)
++ reg |= mask;
++ else
++ reg &= ~mask;
++ bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
++}
++
+ /*
+ * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
+ */
+@@ -317,12 +329,17 @@ static struct clk clk_ipsec = {
+
+ static void pcie_set(struct clk *clk, int enable)
+ {
+- if (BCMCPU_IS_6328())
++ if (BCMCPU_IS_6318()) {
++ bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable);
++ bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable);
++ bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable);
++ } else if (BCMCPU_IS_6328()) {
+ bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+- else if (BCMCPU_IS_6362())
++ } else if (BCMCPU_IS_6362()) {
+ bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
+- else if (BCMCPU_IS_63268())
++ } else if (BCMCPU_IS_63268()) {
+ bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
++ }
+ }
+
+ static struct clk clk_pcie = {
+@@ -393,7 +410,7 @@ struct clk *clk_get(struct device *dev,
+ if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) &&
+ !strcmp(id, "ipsec"))
+ return &clk_ipsec;
+- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) &&
++ if ((BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) &&
+ !strcmp(id, "pcie"))
+ return &clk_pcie;
+ return ERR_PTR(-ENOENT);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,6 +40,12 @@
+ #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
+ BCM_CB_MEM_SIZE - 1)
+
++#define BCM_PCIE_MEM_BASE_PA_6318 0x10200000
++#define BCM_PCIE_MEM_SIZE_6318 (1 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_6318 (BCM_PCIE_MEM_BASE_PA_6318 + \
++ BCM_PCIE_MEM_SIZE_6318 - 1)
++
++
+ #define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000
+ #define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024)
+ #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1661,6 +1661,17 @@
+ * _REG relative to RSET_PCIE
+ *************************************************************************/
+
++#define PCIE_SPECIFIC_REG 0x188
++#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0
++#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2
++#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4
++#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
++#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0
++#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
++#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2
++
+ #define PCIE_CONFIG2_REG 0x408
+ #define CONFIG2_BAR1_SIZE_EN 1
+ #define CONFIG2_BAR1_SIZE_MASK 0xf
+@@ -1706,7 +1717,54 @@
+ #define PCIE_RC_INT_C (1 << 2)
+ #define PCIE_RC_INT_D (1 << 3)
+
+-#define PCIE_DEVICE_OFFSET 0x8000
++#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c
++#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3
++#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0
++#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
++#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
++#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20
++#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
++
++#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c
++#define RC_BAR_CFG_LO_SIZE_256MB 0xd
++#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20
++#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
++
++#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
++#define C2P_BASELIMIT_LIMIT_SHIFT 20
++#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
++#define C2P_BASELIMIT_BASE_SHIFT 4
++#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT)
++
++#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088
++#define BAR1_CFG_REMAP_OFFSET_SHIFT 20
++#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
++#define BAR1_CFG_REMAP_ACCESS_EN 1
++
++#define PCIE_HARD_DEBUG_REG 0x4204
++#define HARD_DEBUG_SERDES_IDDQ (1 << 23)
++
++#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c
++#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0)
++#define CPU_INT_PCIE_INTA (1 << 1)
++#define CPU_INT_PCIE_INTB (1 << 2)
++#define CPU_INT_PCIE_INTC (1 << 3)
++#define CPU_INT_PCIE_INTD (1 << 4)
++#define CPU_INT_PCIE_INTR (1 << 5)
++#define CPU_INT_PCIE_NMI (1 << 6)
++#define CPU_INT_PCIE_UBUS (1 << 7)
++#define CPU_INT_IPI (1 << 8)
++
++#define PCIE_EXT_CFG_INDEX_REG 0x8400
++#define EXT_CFG_FUNC_NUM_SHIFT 12
++#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT)
++#define EXT_CFG_DEV_NUM_SHIFT 15
++#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT)
++#define EXT_CFG_BUS_NUM_SHIFT 20
++#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT)
++
++#define PCIE_DEVICE_OFFSET_6318 0x9000
++#define PCIE_DEVICE_OFFSET_6328 0x8000
+
+ /*************************************************************************
+ * _REG relative to RSET_OTP
+--- a/arch/mips/pci/ops-bcm63xx.c
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -489,8 +489,12 @@ static int bcm63xx_pcie_read(struct pci_
+ if (!bcm63xx_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- if (bus->number == PCIE_BUS_DEVICE)
+- reg += PCIE_DEVICE_OFFSET;
++ if (bus->number == PCIE_BUS_DEVICE) {
++ if (BCMCPU_IS_6318())
++ reg += PCIE_DEVICE_OFFSET_6318;
++ else
++ reg += PCIE_DEVICE_OFFSET_6328;
++ }
+
+ data = bcm_pcie_readl(reg);
+
+@@ -509,8 +513,12 @@ static int bcm63xx_pcie_write(struct pci
+ if (!bcm63xx_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- if (bus->number == PCIE_BUS_DEVICE)
+- reg += PCIE_DEVICE_OFFSET;
++ if (bus->number == PCIE_BUS_DEVICE) {
++ if (BCMCPU_IS_6318())
++ reg += PCIE_DEVICE_OFFSET_6318;
++ else
++ reg += PCIE_DEVICE_OFFSET_6328;
++ }
+
+
+ data = bcm_pcie_readl(reg);
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v
+
+ void __iomem *pci_iospace_start;
+
+-static void __init bcm63xx_reset_pcie(void)
++static void __init bcm63xx_reset_pcie_gen1(void)
+ {
+ u32 val;
+ u32 reg;
+@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo
+ mdelay(200);
+ }
+
+-static struct clk *pcie_clk;
+-
+-static int __init bcm63xx_register_pcie(void)
++static void __init bcm63xx_reset_pcie_gen2(void)
+ {
+ u32 val;
+
+- /* enable clock */
+- pcie_clk = clk_get(NULL, "pcie");
+- if (IS_ERR_OR_NULL(pcie_clk))
+- return -ENODEV;
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
+
+- clk_prepare_enable(pcie_clk);
++ /* reset the PCIe core */
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
++ mdelay(10);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
++ mdelay(10);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
++ mdelay(10);
++ val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG);
++ val &= ~HARD_DEBUG_SERDES_IDDQ;
++ bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG);
++ mdelay(10);
++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
++ mdelay(200);
++}
+
+- bcm63xx_reset_pcie();
++static void __init bcm63xx_init_pcie_gen1(void)
++{
++ u32 val;
+
+ /* configure the PCIe bridge */
+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
+@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie(
+ val |= OPT2_CFG_TYPE1_BD_SEL;
+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
+
++ /* set bar0 to little endian */
++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
++ val |= BASEMASK_REMAP_EN;
++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
++
++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
++}
++
++static void __init bcm63xx_init_pcie_gen2(void)
++{
++ u32 val;
++
++ bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
++ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
++ PCIE_CPU_INT1_MASK_CLEAR_REG);
++
++ val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
++ val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) <<
++ C2P_BASELIMIT_BASE_SHIFT;
++
++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
++
++ /* set bar0 to little endian */
++ val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
++ val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
++ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
++
++ bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG);
++ bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG);
++ bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG);
++
++ bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
++ PCIE_EXT_CFG_INDEX_REG);
++}
++
++static struct clk *pcie_clk;
++
++static int __init bcm63xx_register_pcie(void)
++{
++ u32 val;
++
++ /* enable clock */
++ pcie_clk = clk_get(NULL, "pcie");
++ if (IS_ERR_OR_NULL(pcie_clk))
++ return -ENODEV;
++
++ clk_prepare_enable(pcie_clk);
++
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
++ bcm63xx_reset_pcie_gen1();
++ bcm63xx_init_pcie_gen1();
++ } else {
++ bcm63xx_reset_pcie_gen2();
++ bcm63xx_init_pcie_gen2();
++ }
++
+ /* setup class code as bridge */
+ val = bcm_pcie_readl(PCIE_IDVAL3_REG);
+ val &= ~IDVAL3_CLASS_CODE_MASK;
+@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie(
+ val &= ~CONFIG2_BAR1_SIZE_MASK;
+ bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+
+- /* set bar0 to little endian */
+- val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
+- val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+- val |= BASEMASK_REMAP_EN;
+- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+-
+- val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
+- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+-
+ register_pci_controller(&bcm63xx_pcie_controller);
+
+ return 0;
+@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void)
+ if (!bcm63xx_pci_enabled)
+ return -ENODEV;
+
+- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++ if (BCMCPU_IS_6318()) {
++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318;
++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318;
++ } if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
+ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
+ } else if (BCMCPU_IS_63268()) {
+@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void)
+ }
+
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6318_CPU_ID:
+ case BCM6328_CPU_ID:
+ case BCM6362_CPU_ID:
+ case BCM63268_CPU_ID:
bcm_gpio_writel(val, GPIO_MODE_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -695,6 +695,8 @@
+@@ -767,6 +767,8 @@
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1005,6 +1005,19 @@
+@@ -1077,6 +1077,19 @@
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
static int __init bcm63xx_detect_flash_type(void)
{
u32 val;
-@@ -62,6 +80,11 @@ static int __init bcm63xx_detect_flash_t
+@@ -62,9 +80,15 @@ static int __init bcm63xx_detect_flash_t
switch (bcm63xx_get_cpu_id()) {
+ case BCM6318_CPU_ID:
+ /* only support serial flash */
++ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
+ return BCM63XX_FLASH_TYPE_SERIAL;
case BCM6328_CPU_ID:
val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+ if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
return BCM63XX_FLASH_TYPE_SERIAL;
else
-@@ -80,12 +103,20 @@ static int __init bcm63xx_detect_flash_t
+@@ -83,12 +107,20 @@ static int __init bcm63xx_detect_flash_t
return BCM63XX_FLASH_TYPE_SERIAL;
case BCM6362_CPU_ID:
val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
case STRAPBUS_6368_BOOT_SEL_NAND:
return BCM63XX_FLASH_TYPE_NAND;
-@@ -96,6 +127,11 @@ static int __init bcm63xx_detect_flash_t
+@@ -99,6 +131,11 @@ static int __init bcm63xx_detect_flash_t
}
case BCM63268_CPU_ID:
val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
return BCM63XX_FLASH_TYPE_SERIAL;
else
-@@ -123,8 +159,14 @@ int __init bcm63xx_flash_register(void)
+@@ -126,8 +163,15 @@ int __init bcm63xx_flash_register(void)
return platform_device_register(&mtd_dev);
case BCM63XX_FLASH_TYPE_SERIAL:
- pr_warn("unsupported serial flash detected\n");
- return -ENODEV;
-+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
++ BCMCPU_IS_63268())
+ bcm63xx_spi_flash_info[0].bus_num = 1;
+
+ if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
return -ENODEV;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -746,6 +746,7 @@
+@@ -818,6 +818,7 @@
#define GPIO_STRAPBUS_REG 0x40
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
#define STRAPBUS_6368_BOOT_SEL_NAND 0
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
-@@ -1594,6 +1595,7 @@
+@@ -1667,6 +1668,7 @@
#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
#define MISC_STRAPBUS_6328_REG 0x240
static struct mtd_partition mtd_partitions[] = {
{
.name = "cfe",
-@@ -86,21 +88,24 @@ static int __init bcm63xx_detect_flash_t
+@@ -81,7 +83,8 @@ static int __init bcm63xx_detect_flash_t
+ case BCM6318_CPU_ID:
+ /* only support serial flash */
+ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
+- return BCM63XX_FLASH_TYPE_SERIAL;
++ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
++ break;
+ case BCM6328_CPU_ID:
+ val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+ if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
+@@ -90,21 +93,24 @@ static int __init bcm63xx_detect_flash_t
bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
case BCM6362_CPU_ID:
val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
-@@ -109,9 +114,10 @@ static int __init bcm63xx_detect_flash_t
+@@ -113,9 +119,10 @@ static int __init bcm63xx_detect_flash_t
bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
case BCM6368_CPU_ID:
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
if (val & STRAPBUS_6368_SPI_CLK_FAST)
-@@ -119,11 +125,16 @@ static int __init bcm63xx_detect_flash_t
+@@ -123,11 +130,16 @@ static int __init bcm63xx_detect_flash_t
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
case STRAPBUS_6368_BOOT_SEL_NAND:
}
case BCM63268_CPU_ID:
val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
-@@ -133,22 +144,24 @@ static int __init bcm63xx_detect_flash_t
+@@ -137,22 +149,24 @@ static int __init bcm63xx_detect_flash_t
bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
case BCM63XX_FLASH_TYPE_PARALLEL:
/* read base address of boot chip select (0) */
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-@@ -172,7 +185,7 @@ int __init bcm63xx_flash_register(void)
+@@ -177,7 +191,7 @@ int __init bcm63xx_flash_register(void)
return -ENODEV;
default:
pr_err("flash detection failed for BCM%x: %d\n",
};
static struct spi_board_info bcm63xx_spi_flash_info[] = {
-@@ -154,10 +158,13 @@ static int __init bcm63xx_detect_flash_t
+@@ -159,10 +163,13 @@ static int __init bcm63xx_detect_flash_t
return 0;
}
}
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -158,7 +158,7 @@ static int __init bcm63xx_detect_flash_t
+@@ -163,7 +163,7 @@ static int __init bcm63xx_detect_flash_t
return 0;
}
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_flash.h>
#include <bcm63xx_dev_hsspi.h>
-@@ -174,6 +175,13 @@ int __init bcm63xx_flash_register(int nu
+@@ -179,6 +180,13 @@ int __init bcm63xx_flash_register(int nu
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
projects / openwrt / staging / rmilecki.git / commitdiff