MC_CG_SEQ_DRAMCONF_S0 : MC_CG_SEQ_DRAMCONF_S1;
}
+#if 0
int rv770_read_smc_soft_register(struct radeon_device *rdev,
u16 reg_offset, u32 *value)
{
pi->soft_regs_start + reg_offset,
value, pi->sram_end);
}
+#endif
int rv770_write_smc_soft_register(struct radeon_device *rdev,
u16 reg_offset, u32 value)
return 0;
}
+#if 0
void rv770_dpm_reset_asic(struct radeon_device *rdev)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
if (pi->dcodt)
rv770_program_dcodt_after_state_switch(rdev, boot_ps, boot_ps);
}
+#endif
void rv770_dpm_setup_asic(struct radeon_device *rdev)
{
void rv770_get_engine_memory_ss(struct radeon_device *rdev);
/* smc */
-int rv770_read_smc_soft_register(struct radeon_device *rdev,
- u16 reg_offset, u32 *value);
int rv770_write_smc_soft_register(struct radeon_device *rdev,
u16 reg_offset, u32 value);