drm/amd/powerplay: move the ASIC specific nbio operation out of smu_v11_0.c

This is ASIC specific and should be placed in _ppt.c of each ASIC.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index c6d3bef15320a57eeef096fa5a19451da9600629..5db8c56066ee3b83740dbb011a12e68e1440b14c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -35,6 +35,7 @@
 #include "arcturus_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "arcturus_ppsmc.h"
+#include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "amdgpu_xgmi.h"
 #include <linux/i2c.h>
@@ -2210,6 +2211,18 @@ static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
        i2c_del_adapter(control);
 }
 
+static bool arcturus_is_baco_supported(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
+
+       if (!smu_v11_0_baco_is_support(smu))
+               return false;
+
+       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
 {
        PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -2321,7 +2334,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
        .register_irq_handler = smu_v11_0_register_irq_handler,
        .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
        .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_is_support= arcturus_is_baco_supported,
        .baco_get_state = smu_v11_0_baco_get_state,
        .baco_set_state = smu_v11_0_baco_set_state,
        .baco_enter = smu_v11_0_baco_enter,

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 9c60b38ab53a88afd64efb0877248c6e15488f31..15030284b4446f4d75d67f4d17f24d1f246d7e09 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -28,13 +28,15 @@
 #include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
+#include "soc15_common.h"
 #include "smu_v11_0.h"
 #include "smu11_driver_if_navi10.h"
 #include "atom.h"
 #include "navi10_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "smu_v11_0_ppsmc.h"
-#include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_2_3_offset.h"
+#include "nbio/nbio_2_3_sh_mask.h"
 
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
 
@@ -1985,6 +1987,18 @@ static int navi10_setup_od_limits(struct smu_context *smu) {
        return 0;
 }
 
+static bool navi10_is_baco_supported(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
+
+       if (!smu_v11_0_baco_is_support(smu))
+               return false;
+
+       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
        OverDriveTable_t *od_table, *boot_od_table;
        int ret = 0;
@@ -2361,7 +2375,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .register_irq_handler = smu_v11_0_register_irq_handler,
        .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
        .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_is_support= navi10_is_baco_supported,
        .baco_get_state = smu_v11_0_baco_get_state,
        .baco_set_state = smu_v11_0_baco_set_state,
        .baco_enter = smu_v11_0_baco_enter,

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b60d57ac1cd45fb3c91c9b014f30bcee82742194..541c932a60051bb9c00215ca22e7924892c1d355 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -42,8 +42,6 @@
 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
 #include "asic_reg/mp/mp_11_0_offset.h"
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
-#include "asic_reg/nbio/nbio_7_4_offset.h"
-#include "asic_reg/nbio/nbio_7_4_sh_mask.h"
 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
 
@@ -1662,9 +1660,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v
 
 bool smu_v11_0_baco_is_support(struct smu_context *smu)
 {
-       struct amdgpu_device *adev = smu->adev;
        struct smu_baco_context *smu_baco = &smu->smu_baco;
-       uint32_t val;
        bool baco_support;
 
        mutex_lock(&smu_baco->mutex);
@@ -1679,11 +1675,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
           !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
                return false;
 
-       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-       if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
-               return true;
-
-       return false;
+       return true;
 }
 
 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 49ff3756bd9fc1c6186b54a826e161bfce18598b..3f1044326dcb6b59d2b66e4f48864715adc2a3d5 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -35,6 +35,7 @@
 #include "vega20_ppt.h"
 #include "vega20_pptable.h"
 #include "vega20_ppsmc.h"
+#include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "asic_reg/thm/thm_11_0_2_offset.h"
 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -3174,6 +3175,17 @@ static int vega20_update_pcie_parameters(struct smu_context *smu,
        return ret;
 }
 
+static bool vega20_is_baco_supported(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
+
+       if (!smu_v11_0_baco_is_support(smu))
+               return false;
+
+       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
 
 static const struct pptable_funcs vega20_ppt_funcs = {
        .tables_init = vega20_tables_init,
@@ -3262,7 +3274,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
        .register_irq_handler = smu_v11_0_register_irq_handler,
        .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
        .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-       .baco_is_support= smu_v11_0_baco_is_support,
+       .baco_is_support= vega20_is_baco_supported,
        .baco_get_state = smu_v11_0_baco_get_state,
        .baco_set_state = smu_v11_0_baco_set_state,
        .baco_enter = smu_v11_0_baco_enter,