ath9k_hw: add support for parsing PA predistortion related EEPROM fields
authorFelix Fietkau <nbd@openwrt.org>
Sat, 12 Jun 2010 04:33:59 +0000 (00:33 -0400)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 14 Jun 2010 19:39:32 +0000 (15:39 -0400)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
drivers/net/wireless/ath/ath9k/eeprom.h
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/hw.h

index 23eb60ea54551eee078009418c1159eaffc622f2..343c9a427acb50f9b48abfb778975d6bcde74005 100644 (file)
@@ -67,6 +67,7 @@ static const struct ar9300_eeprom ar9300_default = {
                  * bit2 - enable fastClock - enabled
                  * bit3 - enable doubling - enabled
                  * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
                  */
                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
                .eepromWriteEnableGpio = 3,
@@ -129,9 +130,11 @@ static const struct ar9300_eeprom ar9300_default = {
                .txEndToRxOn = 0x2,
                .txFrameToXpaOn = 0xe,
                .thresh62 = 28,
-               .futureModal = { /* [32] */
+               .papdRateMaskHt20 = LE32(0x80c080),
+               .papdRateMaskHt40 = LE32(0x80c080),
+               .futureModal = {
                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+                       0, 0, 0, 0, 0, 0, 0, 0
                },
         },
        .calFreqPier2G = {
@@ -326,9 +329,11 @@ static const struct ar9300_eeprom ar9300_default = {
                .txEndToRxOn = 0x2,
                .txFrameToXpaOn = 0xe,
                .thresh62 = 28,
+               .papdRateMaskHt20 = LE32(0xf0e0e0),
+               .papdRateMaskHt40 = LE32(0xf0e0e0),
                .futureModal = {
                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+                       0, 0, 0, 0, 0, 0, 0, 0
                },
         },
        .calFreqPier5G = {
@@ -644,6 +649,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                return (pBase->featureEnable & 0x10) >> 4;
        case EEP_SWREG:
                return le32_to_cpu(pBase->swreg);
+       case EEP_PAPRD:
+               return !!(pBase->featureEnable & BIT(5));
        default:
                return 0;
        }
index 23fb353c3bba502f3eeacf1eaa0fbbea6d19c715..3c533bb983c72859c9fbea4563070f387747506e 100644 (file)
@@ -234,7 +234,9 @@ struct ar9300_modal_eep_header {
        u8 txEndToRxOn;
        u8 txFrameToXpaOn;
        u8 thresh62;
-       u8 futureModal[32];
+       __le32 papdRateMaskHt20;
+       __le32 papdRateMaskHt40;
+       u8 futureModal[24];
 } __packed;
 
 struct ar9300_cal_data_per_freq_op_loop {
index 7da7d73c08474675fb25b2c38d43b5e550c367a8..bdd8aa054b80bffa98ab56fd773a133a518aede2 100644 (file)
@@ -263,7 +263,8 @@ enum eeprom_param {
        EEP_PWR_TABLE_OFFSET,
        EEP_DRIVE_STRENGTH,
        EEP_INTERNAL_REGULATOR,
-       EEP_SWREG
+       EEP_SWREG,
+       EEP_PAPRD,
 };
 
 enum ar5416_rates {
index 83e04613f785e1575e4193e08af32beb12a5aaa0..5a2e72aaf49019b7318eea5f2cbc92b5682ea946 100644 (file)
@@ -2235,6 +2235,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                pCap->rx_status_len = sizeof(struct ar9003_rxs);
                pCap->tx_desc_len = sizeof(struct ar9003_txc);
                pCap->txs_len = sizeof(struct ar9003_txs);
+               if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
+                       pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
        } else {
                pCap->tx_desc_len = sizeof(struct ath_desc);
                if (AR_SREV_9280_20(ah) &&
index 09dd7be549a0dab4febf13845da8798d4ad3478c..9d092168855b600fd6da989e4c7b9eb72b9a237b 100644 (file)
@@ -200,6 +200,7 @@ enum ath9k_hw_caps {
        ATH9K_HW_CAP_LDPC                       = BIT(19),
        ATH9K_HW_CAP_FASTCLOCK                  = BIT(20),
        ATH9K_HW_CAP_SGI_20                     = BIT(21),
+       ATH9K_HW_CAP_PAPRD                      = BIT(22),
 };
 
 enum ath9k_capability_type {