mediatek: pull in some fixes fromt he latest SDK

Signed-off-by: John Crispin <john@phrozen.org>

diff --git a/target/linux/mediatek/patches-5.4/0503-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.4/0503-crypto-fix-eip97-cache-incoherent.patch
new file mode 100644 (file)
index 0000000..bb2bceb
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0503-crypto-fix-eip97-cache-incoherent.patch
@@ -0,0 +1,26 @@
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -722,6 +722,9 @@
+ /* Priority we use for advertising our algorithms */
+ #define SAFEXCEL_CRA_PRIORITY         300
+ 
++/* System cache line size */
++#define SYSTEM_CACHELINE_SIZE         64
++
+ /* SM3 digest result for zero length message */
+ #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
+                               "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
+--- a/drivers/crypto/inside-secure/safexcel_hash.c
++++ b/drivers/crypto/inside-secure/safexcel_hash.c
+@@ -57,9 +57,9 @@
+       u8 block_sz;    /* block size, only set once */
+       u8 digest_sz;   /* output digest size, only set once */
+       __le32 state[SHA3_512_BLOCK_SIZE /
+-                   sizeof(__le32)] __aligned(sizeof(__le32));
++                   sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
+ 
+-      u64 len;
++      u64 len __aligned(SYSTEM_CACHELINE_SIZE);
+       u64 processed;
+ 
+       u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));

diff --git a/target/linux/mediatek/patches-5.4/1002-eth-mtk-performance-tuning.patch b/target/linux/mediatek/patches-5.4/1002-eth-mtk-performance-tuning.patch
new file mode 100644 (file)
index 0000000..6d1d5e8
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/1002-eth-mtk-performance-tuning.patch
@@ -0,0 +1,60 @@
+diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c      2020-08-25 14:57:28.403764254 +0800
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c      2020-08-25 14:57:39.803438475 +0800
+@@ -2193,7 +2193,7 @@
+       if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
+               mtk_w32(eth,
+                       MTK_TX_DMA_EN |
+-                      MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
++                      MTK_DMA_SIZE_32DWORDS | MTK_NDP_CO_PRO |
+                       MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
+                       MTK_RX_BT_32DWORDS,
+                       MTK_QDMA_GLO_CFG);
+@@ -2434,11 +2434,10 @@
+       /* Enable RX VLan Offloading */
+       mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
+ 
+-      /* enable interrupt delay for RX */
+-      mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
++      /* enable interrupt delay for RX/TX */
++      mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_DELAY_INT);
++      mtk_w32(eth, 0x8f0f8f0f, MTK_QDMA_DELAY_INT);
+ 
+-      /* disable delay and normal interrupt */
+-      mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+       mtk_tx_irq_disable(eth, ~0);
+       mtk_rx_irq_disable(eth, ~0);
+ 
+diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h      2020-08-25 14:57:22.939920398 +0800
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h      2020-08-25 14:57:43.359336855 +0800
+@@ -19,8 +19,8 @@
+ #define MTK_QDMA_PAGE_SIZE    2048
+ #define       MTK_MAX_RX_LENGTH       1536
+ #define MTK_TX_DMA_BUF_LEN    0x3fff
+-#define MTK_DMA_SIZE          256
+-#define MTK_NAPI_WEIGHT               64
++#define MTK_DMA_SIZE          2048
++#define MTK_NAPI_WEIGHT               256
+ #define MTK_MAC_COUNT         2
+ #define MTK_RX_ETH_HLEN               (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
+ #define MTK_RX_HLEN           (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
+@@ -198,6 +198,7 @@
+ #define MTK_NDP_CO_PRO                BIT(10)
+ #define MTK_TX_WB_DDONE               BIT(6)
+ #define MTK_DMA_SIZE_16DWORDS (2 << 4)
++#define MTK_DMA_SIZE_32DWORDS (3 << 4)
+ #define MTK_RX_DMA_BUSY               BIT(3)
+ #define MTK_TX_DMA_BUSY               BIT(1)
+ #define MTK_RX_DMA_EN         BIT(2)
+@@ -228,8 +229,8 @@
+ #define MTK_TX_DONE_INT1      BIT(1)
+ #define MTK_TX_DONE_INT0      BIT(0)
+ #define MTK_RX_DONE_INT               MTK_RX_DONE_DLY
+-#define MTK_TX_DONE_INT               (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
+-                               MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
++#define MTK_TX_DONE_DLY         BIT(28)
++#define MTK_TX_DONE_INT         MTK_TX_DONE_DLY
+ 
+ /* QDMA Interrupt grouping registers */
+ #define MTK_QDMA_INT_GRP1     0x1a20

diff --git a/target/linux/mediatek/patches-5.4/1003-dts-mt7622-rfb-change-to-ax-mtd-layout.patch b/target/linux/mediatek/patches-5.4/1003-dts-mt7622-rfb-change-to-ax-mtd-layout.patch
new file mode 100644 (file)
index 0000000..eba3caf
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/1003-dts-mt7622-rfb-change-to-ax-mtd-layout.patch
@@ -0,0 +1,23 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts     2020-07-16 16:31:01.073767264 +0800
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts     2020-07-16 16:33:02.518867067 +0800
+@@ -579,17 +579,17 @@
+ 
+                       factory: partition@1c0000 {
+                               label = "Factory";
+-                              reg = <0x1c0000 0x0040000>;
++                              reg = <0x1c0000 0x0100000>;
+                       };
+ 
+                       partition@200000 {
+                               label = "firmware";
+-                              reg = <0x200000 0x2000000>;
++                              reg = <0x2c0000 0x2000000>;
+                       };
+ 
+                       partition@2200000 {
+                               label = "User_data";
+-                              reg = <0x2200000 0x4000000>;
++                              reg = <0x22c0000 0x4000000>;
+                       };
+               };
+       };