drm/i915: Further assorted dev_priv cleanups

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9eabf54a381e6bb486f31cdadc5568b94118cf02..89216d786a76949e05fc82aa44ef7f67fc83a916 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2376,7 +2376,7 @@ struct drm_i915_cmd_table {
 #define INTEL_DEVID(dev_priv)  ((dev_priv)->info.device_id)
 
 #define REVID_FOREVER          0xff
-#define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
+#define INTEL_REVID(dev_priv)  ((dev_priv)->drm.pdev->revision)
 
 #define GEN_FOREVER (0)
 /*
@@ -2604,13 +2604,13 @@ struct drm_i915_cmd_table {
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev)           (INTEL_INFO(dev)->has_guc)
-#define HAS_GUC_UCODE(dev)     (HAS_GUC(dev))
-#define HAS_GUC_SCHED(dev)     (HAS_GUC(dev))
+#define HAS_GUC(dev_priv)      ((dev_priv)->info.has_guc)
+#define HAS_GUC_UCODE(dev_priv)        (HAS_GUC(dev_priv))
+#define HAS_GUC_SCHED(dev_priv)        (HAS_GUC(dev_priv))
 
-#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
+#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
-#define HAS_POOLED_EU(dev)     (INTEL_INFO(dev)->has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv)        ((dev_priv)->info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK               0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE           0x3b00

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 807c743daa8f6095345e16c4bc7a4471c99eee28..e804cb2fa57e3964cae8c004606c160cc4863e3f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1624,7 +1624,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
        }
 
        if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
-               if (!HAS_RESOURCE_STREAMER(dev)) {
+               if (!HAS_RESOURCE_STREAMER(dev_priv)) {
                        DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
                        return -EINVAL;
                }

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 285ee1e4352a8be5aa5ea64b0a4f1216fbaa5c52..cb8a75f6ca167911d8e0c60194f0faafd2861596 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4145,7 +4145,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
        INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
        INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
-       if (HAS_GUC_SCHED(dev))
+       if (HAS_GUC_SCHED(dev_priv))
                dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
 
        /* Let's track the enabled rps events */

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1aa85236b78865afdd7f6e04b1fe9e0e812973d3..34d6ad2cf7c1db718ebb5c46b0b99580675e12a6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -566,7 +566,7 @@ fail:
                ret = 0;
        }
 
-       if (err == 0 && !HAS_GUC_UCODE(dev))
+       if (err == 0 && !HAS_GUC_UCODE(dev_priv))
                ;       /* Don't mention the GuC! */
        else if (err == 0)
                DRM_INFO("GuC firmware load skipped\n");
@@ -725,18 +725,18 @@ void intel_guc_init(struct drm_device *dev)
        struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
        const char *fw_path;
 
-       if (!HAS_GUC(dev)) {
+       if (!HAS_GUC(dev_priv)) {
                i915.enable_guc_loading = 0;
                i915.enable_guc_submission = 0;
        } else {
                /* A negative value means "use platform default" */
                if (i915.enable_guc_loading < 0)
-                       i915.enable_guc_loading = HAS_GUC_UCODE(dev);
+                       i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
                if (i915.enable_guc_submission < 0)
-                       i915.enable_guc_submission = HAS_GUC_SCHED(dev);
+                       i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
        }
 
-       if (!HAS_GUC_UCODE(dev)) {
+       if (!HAS_GUC_UCODE(dev_priv)) {
                fw_path = NULL;
        } else if (IS_SKYLAKE(dev_priv)) {
                fw_path = I915_SKL_GUC_UCODE;