x86/cpuid: Cleanup cpuid_regs definitions

cpuid_regs is defined multiple times as structure and enum. Rename the enum
and move all of it to processor.h so we don't end up with more instances.

Rename the misnomed register enumeration from CR_* to the obvious CPUID_*.

[ tglx: Rewrote changelog ]

Signed-off-by: He Chen <he.chen@linux.intel.com>
Reviewed-by: Borislav Petkov <bp@alien8.de>
Cc: Luwei Kang <luwei.kang@intel.com>
Cc: kvm@vger.kernel.org
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Piotr Luc <Piotr.Luc@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: http://lkml.kernel.org/r/1478856336-9388-2-git-send-email-he.chen@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index c5047b8f777b27e918b3c5e0982dd274cf652dd0..1c1b9fe705c84d218cbbf3aeea92edde4bbc40cd 100644 (file)
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -36,13 +36,6 @@ static DEFINE_PER_CPU(struct pt, pt_ctx);
 
 static struct pt_pmu pt_pmu;
 
-enum cpuid_regs {
-       CR_EAX = 0,
-       CR_ECX,
-       CR_EDX,
-       CR_EBX
-};
-
 /*
  * Capabilities of Intel PT hardware, such as number of address bits or
  * supported output schemes, are cached and exported to userspace as "caps"
@@ -64,21 +57,21 @@ static struct pt_cap_desc {
        u8              reg;
        u32             mask;
 } pt_caps[] = {
-       PT_CAP(max_subleaf,             0, CR_EAX, 0xffffffff),
-       PT_CAP(cr3_filtering,           0, CR_EBX, BIT(0)),
-       PT_CAP(psb_cyc,                 0, CR_EBX, BIT(1)),
-       PT_CAP(ip_filtering,            0, CR_EBX, BIT(2)),
-       PT_CAP(mtc,                     0, CR_EBX, BIT(3)),
-       PT_CAP(ptwrite,                 0, CR_EBX, BIT(4)),
-       PT_CAP(power_event_trace,       0, CR_EBX, BIT(5)),
-       PT_CAP(topa_output,             0, CR_ECX, BIT(0)),
-       PT_CAP(topa_multiple_entries,   0, CR_ECX, BIT(1)),
-       PT_CAP(single_range_output,     0, CR_ECX, BIT(2)),
-       PT_CAP(payloads_lip,            0, CR_ECX, BIT(31)),
-       PT_CAP(num_address_ranges,      1, CR_EAX, 0x3),
-       PT_CAP(mtc_periods,             1, CR_EAX, 0xffff0000),
-       PT_CAP(cycle_thresholds,        1, CR_EBX, 0xffff),
-       PT_CAP(psb_periods,             1, CR_EBX, 0xffff0000),
+       PT_CAP(max_subleaf,             0, CPUID_EAX, 0xffffffff),
+       PT_CAP(cr3_filtering,           0, CPUID_EBX, BIT(0)),
+       PT_CAP(psb_cyc,                 0, CPUID_EBX, BIT(1)),
+       PT_CAP(ip_filtering,            0, CPUID_EBX, BIT(2)),
+       PT_CAP(mtc,                     0, CPUID_EBX, BIT(3)),
+       PT_CAP(ptwrite,                 0, CPUID_EBX, BIT(4)),
+       PT_CAP(power_event_trace,       0, CPUID_EBX, BIT(5)),
+       PT_CAP(topa_output,             0, CPUID_ECX, BIT(0)),
+       PT_CAP(topa_multiple_entries,   0, CPUID_ECX, BIT(1)),
+       PT_CAP(single_range_output,     0, CPUID_ECX, BIT(2)),
+       PT_CAP(payloads_lip,            0, CPUID_ECX, BIT(31)),
+       PT_CAP(num_address_ranges,      1, CPUID_EAX, 0x3),
+       PT_CAP(mtc_periods,             1, CPUID_EAX, 0xffff0000),
+       PT_CAP(cycle_thresholds,        1, CPUID_EBX, 0xffff),
+       PT_CAP(psb_periods,             1, CPUID_EBX, 0xffff0000),
 };
 
 static u32 pt_cap_get(enum pt_capabilities cap)
@@ -213,10 +206,10 @@ static int __init pt_pmu_hw_init(void)
 
        for (i = 0; i < PT_CPUID_LEAVES; i++) {
                cpuid_count(20, i,
-                           &pt_pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
-                           &pt_pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
-                           &pt_pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
-                           &pt_pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
+                           &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
+                           &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
+                           &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
+                           &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
        }
 
        ret = -ENOMEM;

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 984a7bf17f6a7295c3a7c8531e68cb807a722c35..8f6ac5be84b7c3900ceb4db396f49ffa09140ab4 100644 (file)
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -137,6 +137,17 @@ struct cpuinfo_x86 {
        u32                     microcode;
 };
 
+struct cpuid_regs {
+       u32 eax, ebx, ecx, edx;
+};
+
+enum cpuid_regs_idx {
+       CPUID_EAX = 0,
+       CPUID_EBX,
+       CPUID_ECX,
+       CPUID_EDX,
+};
+
 #define X86_VENDOR_INTEL       0
 #define X86_VENDOR_CYRIX       1
 #define X86_VENDOR_AMD         2

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 1db8dc490b665e751f43f3411cc21079eea75ae2..dbb470e839f88ad96d481b30998dca63db41b54c 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -17,13 +17,6 @@ struct cpuid_bit {
        u32 sub_leaf;
 };
 
-enum cpuid_regs {
-       CR_EAX = 0,
-       CR_ECX,
-       CR_EDX,
-       CR_EBX
-};
-
 void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
 {
        u32 max_level;
@@ -31,14 +24,14 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
        const struct cpuid_bit *cb;
 
        static const struct cpuid_bit cpuid_bits[] = {
-               { X86_FEATURE_INTEL_PT,         CR_EBX,25, 0x00000007, 0 },
-               { X86_FEATURE_AVX512_4VNNIW,    CR_EDX, 2, 0x00000007, 0 },
-               { X86_FEATURE_AVX512_4FMAPS,    CR_EDX, 3, 0x00000007, 0 },
-               { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
-               { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
-               { X86_FEATURE_HW_PSTATE,        CR_EDX, 7, 0x80000007, 0 },
-               { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
-               { X86_FEATURE_PROC_FEEDBACK,    CR_EDX,11, 0x80000007, 0 },
+               { X86_FEATURE_INTEL_PT,         CPUID_EBX, 25, 0x00000007, 0 },
+               { X86_FEATURE_AVX512_4VNNIW,    CPUID_EDX,  2, 0x00000007, 0 },
+               { X86_FEATURE_AVX512_4FMAPS,    CPUID_EDX,  3, 0x00000007, 0 },
+               { X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
+               { X86_FEATURE_EPB,              CPUID_ECX,  3, 0x00000006, 0 },
+               { X86_FEATURE_HW_PSTATE,        CPUID_EDX,  7, 0x80000007, 0 },
+               { X86_FEATURE_CPB,              CPUID_EDX,  9, 0x80000007, 0 },
+               { X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
                { 0, 0, 0, 0, 0 }
        };
 
@@ -50,8 +43,9 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                    max_level > (cb->level | 0xffff))
                        continue;
 
-               cpuid_count(cb->level, cb->sub_leaf, &regs[CR_EAX],
-                           &regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);
+               cpuid_count(cb->level, cb->sub_leaf, &regs[CPUID_EAX],
+                           &regs[CPUID_EBX], &regs[CPUID_ECX],
+                           &regs[CPUID_EDX]);
 
                if (regs[cb->reg] & (1 << cb->bit))
                        set_cpu_cap(c, cb->feature);

diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 2836de390f95cdad34ff11331d9f0afd8df08998..9095c80723d6be01e4fbe378ef4e0a5772f1c6b4 100644 (file)
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -46,10 +46,6 @@
 
 static struct class *cpuid_class;
 
-struct cpuid_regs {
-       u32 eax, ebx, ecx, edx;
-};
-
 static void cpuid_smp_cpuid(void *cmd_block)
 {
        struct cpuid_regs *cmd = (struct cpuid_regs *)cmd_block;