Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
#PBL preamble and RCW header for T1023RDB
aa55aa55 010e0100
#SerDes Protocol: 0x77
-#Core/DDR: 1400Mhz/1600MT/s with single source clock
-0810000e 00000000 00000000 00000000
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
3b800003 00000012 e8104000 21000000
00000000 00000000 00000000 00022800
00000130 04020200 00000000 00000006