drm/amd/pp: Remove wrong code in fiji_start_smu

HW CG feature will be enabled after hw ip initialized

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index ec14798e87b60af20f31ea077545d9e048a0dded..b6b62a79c8bb8f103a7b20a89ab6d723dafded6f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
                        hwmgr->avfs_supported = false;
        }
 
-       /* To initialize all clock gating before RLC loaded and running.*/
-       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
-                       AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
-       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
-                       AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
-       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
-                       AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
-       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
-                       AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
-
        /* Setup SoftRegsStart here for register lookup in case
         * DummyBackEnd is used and ProcessFirmwareHeader is not executed
         */