drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR

On Baytail, notably, we can still detect missed interrupt syndrome
(where we never spot a completed request). In this case, it can be
alleviated by always keeping the interrupt unmasked, implying that the
interrupt is being lost in the window after modifying the IMR. (This is
the reason we still have the posting reads on enable_irq, if we remove
them we miss interrupts!) Having narrowed the issue down to the IMR,
rather than keeping it always enabled, applying the usual posting
read/flush of the RING_IMR before unmasking the GT IMR also seems to
prevent the missed interrupt. So be it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190102163524.19353-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8967dcb5f58faec72f886d3a47fd8a6ac3c13c70..3d5d6b908148fc866e4e17924198ef3366cdfb37 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -974,6 +974,10 @@ gen6_irq_enable(struct intel_engine_cs *engine)
        I915_WRITE_IMR(engine,
                       ~(engine->irq_enable_mask |
                         engine->irq_keep_mask));
+
+       /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
+       POSTING_READ_FW(RING_IMR(engine->mmio_base));
+
        gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 }