drm/amd/display: Fixes for some MPO cases
authorIlya Bakoulin <Ilya.Bakoulin@amd.com>
Wed, 26 Jun 2019 18:52:46 +0000 (14:52 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 18 Jul 2019 19:27:25 +0000 (14:27 -0500)
[Why]
Alpha could be improperly applied (only affecting half the
frame) for some source pixel formats.

[How]
Change how alpha is enabled in MPC/DPP LB and change the
bottom plane blend mode in MPC.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

index 0bca011ed7c9b34dc412cdb1c2b8f108c5bfd6f0..4f7a10390c57102b25830fe758a256cc8b7741d8 100644 (file)
@@ -211,7 +211,7 @@ struct mpcc *mpc1_insert_plane(
        } else {
                new_mpcc->mpcc_bot = NULL;
                REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
-               REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
+               REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
        }
        REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
        REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
index 64ebfdbbba9bffa6bcd20433441a5bba133aa6d4..566cd4cdfef4b76b307d8823b35944dd83d2a595 100644 (file)
@@ -1863,7 +1863,7 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct mpcc_blnd_cfg blnd_cfg = { {0} };
-       bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+       bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
        int mpcc_id;
        struct mpcc *new_mpcc;
        struct mpc *mpc = dc->res_pool->mpc;