drm/amd/amdgpu: re-factor debugfs wave reader

Move IP version specific code into a callback.

Also add support for gfx7 devices.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1800ea139c98761fad93b3e7ebe1d625e55b41b1..217df2459a980550d191bdbbde7094fc5e409b94 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -840,6 +840,7 @@ struct amdgpu_gfx_funcs {
        /* get the gpu clock counter */
        uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
        void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
+       void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
 };
 
 struct amdgpu_gfx {

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cd44364267f7d8a5225ad3a8a47d3f4ae891553f..b0c7cb7973006f114c05927825adf6fd3cbbf9b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2966,19 +2966,13 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
        return !r ? 4 : r;
 }
 
-static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
-{
-       WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
-       return RREG32(SQ_DATA);
-}
-
 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
                                        size_t size, loff_t *pos)
 {
        struct amdgpu_device *adev = f->f_inode->i_private;
        int r, x;
        ssize_t result=0;
-       uint32_t offset, se, sh, cu, wave, simd, data[16];
+       uint32_t offset, se, sh, cu, wave, simd, data[32];
 
        if (size & 3 || *pos & 3)
                return -EINVAL;
@@ -2990,25 +2984,14 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
        cu = ((*pos >> 23) & 0xFF);
        wave = ((*pos >> 31) & 0xFF);
        simd = ((*pos >> 37) & 0xFF);
-       *pos &= 0x7F;
 
        /* switch to the specific se/sh/cu */
        mutex_lock(&adev->grbm_idx_mutex);
        amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 
        x = 0;
-       if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
-               /* type 0 wave data */
-               data[x++] = 0;
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
-               data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);
-       }
+       if (adev->gfx.funcs->read_wave_data)
+               adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
 
        amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
        mutex_unlock(&adev->grbm_idx_mutex);
@@ -3016,17 +2999,17 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
        if (!x)
                return -EINVAL;
 
-       while (size && (*pos < x * 4)) {
+       while (size && (offset < x * 4)) {
                uint32_t value;
 
-               value = data[*pos >> 2];
+               value = data[offset >> 2];
                r = put_user(value, (uint32_t *)buf);
                if (r)
                        return r;
 
                result += 4;
                buf += 4;
-               *pos += 4;
+               offset += 4;
                size -= 4;
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index bc6ccd05010ff7bc5a101348d33fb2689d6a0dca..91176005eaffd3f6cdd45ede5b5353b9b07a1cce 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4357,9 +4357,34 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
 }
 
+static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
+{
+       WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
+       return RREG32(mmSQ_IND_DATA);
+}
+
+static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
+{
+       /* type 0 wave data */
+       dst[(*no_fields)++] = 0;
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
+}
+
 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
        .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
        .select_se_sh = &gfx_v7_0_select_se_sh,
+       .read_wave_data = &gfx_v7_0_read_wave_data,
 };
 
 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 27b3de44add7a08c5f839dd93c5e8014f2093376..eeb522c0de0bcb763d3c3ee612efcb600fccd9b7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5441,9 +5441,35 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
 }
 
+static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
+{
+       WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
+       return RREG32(mmSQ_IND_DATA);
+}
+
+static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
+{
+       /* type 0 wave data */
+       dst[(*no_fields)++] = 0;
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
+       dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
+}
+
+
 static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
        .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
        .select_se_sh = &gfx_v8_0_select_se_sh,
+       .read_wave_data = &gfx_v8_0_read_wave_data,
 };
 
 static int gfx_v8_0_early_init(void *handle)