drm/nouveau/disp/nv50-: simplify definition of overlay channels
authorBen Skeggs <bskeggs@redhat.com>
Tue, 8 May 2018 10:39:46 +0000 (20:39 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 18 May 2018 05:01:20 +0000 (15:01 +1000)
Introduces a new method of defining channels available from the display,
common to all channel types, allowing for more flexibility in available
channel types/counts, and reducing the amount of boiler-plate required.

This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
23 files changed:
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt215.c [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h

index 48ce6699183e0fed362b9f8c50f2be79428360ce..67861f2ac2a40ff0055c2ca5797b8ee4ef1d3dae 100644 (file)
@@ -96,7 +96,6 @@ nvkm-y += nvkm/engine/disp/coregp102.o
 nvkm-y += nvkm/engine/disp/ovlynv50.o
 nvkm-y += nvkm/engine/disp/ovlyg84.o
 nvkm-y += nvkm/engine/disp/ovlygt200.o
-nvkm-y += nvkm/engine/disp/ovlygt215.o
 nvkm-y += nvkm/engine/disp/ovlygf119.o
 nvkm-y += nvkm/engine/disp/ovlygk104.o
 nvkm-y += nvkm/engine/disp/ovlygp102.o
index c9dc58ce47dd25c6e96def060a2063d7e008010f..b222a1daec407c41a71c46b3b0bd7d194a45cae1 100644 (file)
@@ -5,6 +5,7 @@
 #include <core/object.h>
 #include "nv50.h"
 struct nv50_disp_root;
+struct nv50_disp_dmac_func;
 
 struct nv50_disp_chan {
        const struct nv50_disp_chan_func *func;
@@ -49,6 +50,30 @@ void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
 
 extern const struct nvkm_event_func gf119_disp_chan_uevent;
 
+int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
+                       const struct nv50_disp_chan_mthd *,
+                       struct nv50_disp *, int chid,
+                       const struct nvkm_oclass *, void *argv, u32 argc,
+                       struct nvkm_object **);
+
+int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                      struct nv50_disp *, struct nvkm_object **);
+
+int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                     struct nv50_disp *, struct nvkm_object **);
+
+int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                       struct nv50_disp *, struct nvkm_object **);
+
+int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                       struct nv50_disp *, struct nvkm_object **);
+
+int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                       struct nv50_disp *, struct nvkm_object **);
+
+int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
+                       struct nv50_disp *, struct nvkm_object **);
+
 struct nv50_disp_mthd_list {
        u32 mthd;
        u32 addr;
@@ -81,7 +106,6 @@ extern const struct nv50_disp_chan_mthd g84_disp_core_chan_mthd;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
 extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
 extern const struct nv50_disp_chan_mthd g84_disp_base_chan_mthd;
-extern const struct nv50_disp_chan_mthd g84_disp_ovly_chan_mthd;
 
 extern const struct nv50_disp_chan_mthd g94_disp_core_chan_mthd;
 
@@ -92,7 +116,7 @@ extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_pior;
 extern const struct nv50_disp_chan_mthd gf119_disp_base_chan_mthd;
 
 extern const struct nv50_disp_chan_mthd gk104_disp_core_chan_mthd;
-extern const struct nv50_disp_chan_mthd gk104_disp_ovly_chan_mthd;
+extern const struct nv50_disp_chan_mthd gk104_disp_ovly_mthd;
 
 struct nv50_disp_pioc_oclass {
        int (*ctor)(const struct nv50_disp_chan_func *,
index ca323864ebfec2945dc3ee1b66ca6e198f0588aa..45caaee86744324822b717808b7568a61fba3399 100644 (file)
@@ -55,37 +55,26 @@ int nv50_disp_base_new(const struct nv50_disp_dmac_func *,
                       struct nv50_disp_root *, int chid,
                       const struct nvkm_oclass *oclass, void *data, u32 size,
                       struct nvkm_object **);
-int nv50_disp_ovly_new(const struct nv50_disp_dmac_func *,
-                      const struct nv50_disp_chan_mthd *,
-                      struct nv50_disp_root *, int chid,
-                      const struct nvkm_oclass *oclass, void *data, u32 size,
-                      struct nvkm_object **);
 
 extern const struct nv50_disp_dmac_oclass nv50_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass nv50_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass nv50_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass g84_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass g84_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass g84_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass g94_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt200_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gt200_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gt200_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gt215_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gt215_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gt215_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gf119_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gf119_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gf119_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk104_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gk104_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gk104_disp_ovly_oclass;
 
 extern const struct nv50_disp_dmac_oclass gk110_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gk110_disp_base_oclass;
@@ -98,5 +87,4 @@ extern const struct nv50_disp_dmac_oclass gp100_disp_core_oclass;
 
 extern const struct nv50_disp_dmac_oclass gp102_disp_core_oclass;
 extern const struct nv50_disp_dmac_oclass gp102_disp_base_oclass;
-extern const struct nv50_disp_dmac_oclass gp102_disp_ovly_oclass;
 #endif
index db6234eebc61a24488529393c46a29847d839589..6b55cf483fe2a977c05aa2d2a97b720effc40b65 100644 (file)
@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 g84_disp_ovly_mthd_base = {
@@ -54,8 +51,8 @@ g84_disp_ovly_mthd_base = {
        }
 };
 
-const struct nv50_disp_chan_mthd
-g84_disp_ovly_chan_mthd = {
+static const struct nv50_disp_chan_mthd
+g84_disp_ovly_mthd = {
        .name = "Overlay",
        .addr = 0x000540,
        .prev = 0x000004,
@@ -65,13 +62,10 @@ g84_disp_ovly_chan_mthd = {
        }
 };
 
-const struct nv50_disp_dmac_oclass
-g84_disp_ovly_oclass = {
-       .base.oclass = G82_DISP_OVERLAY_CHANNEL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &nv50_disp_dmac_func,
-       .mthd = &g84_disp_ovly_chan_mthd,
-       .chid = 3,
-};
+int
+g84_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                 struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &g84_disp_ovly_mthd,
+                                  disp, 3, oclass, argv, argc, pobject);
+}
index 5985879abd239e0937ad9c399e6e7fc2c8bcfdfd..30901caf75dc39f336b43c7e46c4d9d6b8b0004c 100644 (file)
@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gf119_disp_ovly_mthd_base = {
@@ -79,7 +76,7 @@ gf119_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-gf119_disp_ovly_chan_mthd = {
+gf119_disp_ovly_mthd = {
        .name = "Overlay",
        .addr = 0x001000,
        .prev = -0x020000,
@@ -89,13 +86,10 @@ gf119_disp_ovly_chan_mthd = {
        }
 };
 
-const struct nv50_disp_dmac_oclass
-gf119_disp_ovly_oclass = {
-       .base.oclass = GF110_DISP_OVERLAY_CONTROL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &gf119_disp_dmac_func,
-       .mthd = &gf119_disp_ovly_chan_mthd,
-       .chid = 5,
-};
+int
+gf119_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                   struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gf119_disp_ovly_mthd,
+                                  disp, 5, oclass, argv, argc, pobject);
+}
index 2f0220b39f3469ba146a73efd94307c6b281d3b7..682c146c39d4e1dfed5eb4a8831a5432ef15b044 100644 (file)
@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gk104_disp_ovly_mthd_base = {
@@ -81,7 +78,7 @@ gk104_disp_ovly_mthd_base = {
 };
 
 const struct nv50_disp_chan_mthd
-gk104_disp_ovly_chan_mthd = {
+gk104_disp_ovly_mthd = {
        .name = "Overlay",
        .addr = 0x001000,
        .prev = -0x020000,
@@ -91,13 +88,10 @@ gk104_disp_ovly_chan_mthd = {
        }
 };
 
-const struct nv50_disp_dmac_oclass
-gk104_disp_ovly_oclass = {
-       .base.oclass = GK104_DISP_OVERLAY_CONTROL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &gf119_disp_dmac_func,
-       .mthd = &gk104_disp_ovly_chan_mthd,
-       .chid = 5,
-};
+int
+gk104_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                   struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gk104_disp_ovly_mthd,
+                                  disp, 5, oclass, argv, argc, pobject);
+}
index 589bd2f12b4137075577213653aa342483ff9def..bcc5ac40f6f9559b0eec670826d4171b36f81b7b 100644 (file)
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
 
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gp102_disp_ovly_oclass = {
-       .base.oclass = GK104_DISP_OVERLAY_CONTROL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &gp102_disp_dmac_func,
-       .mthd = &gk104_disp_ovly_chan_mthd,
-       .chid = 5,
-};
+int
+gp102_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                   struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&gp102_disp_dmac_func, &gk104_disp_ovly_mthd,
+                                  disp, 5, oclass, argv, argc, pobject);
+}
index f858053db83dac692ed8e4ac9c2bb05744818fd7..655deb0d2fa0d1da9581537fab1e14402d25c75f 100644 (file)
@@ -22,9 +22,6 @@
  * Authors: Ben Skeggs
  */
 #include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
 
 static const struct nv50_disp_mthd_list
 gt200_disp_ovly_mthd_base = {
@@ -58,7 +55,7 @@ gt200_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-gt200_disp_ovly_chan_mthd = {
+gt200_disp_ovly_mthd = {
        .name = "Overlay",
        .addr = 0x000540,
        .prev = 0x000004,
@@ -68,13 +65,10 @@ gt200_disp_ovly_chan_mthd = {
        }
 };
 
-const struct nv50_disp_dmac_oclass
-gt200_disp_ovly_oclass = {
-       .base.oclass = GT200_DISP_OVERLAY_CHANNEL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &nv50_disp_dmac_func,
-       .mthd = &gt200_disp_ovly_chan_mthd,
-       .chid = 3,
-};
+int
+gt200_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                   struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &gt200_disp_ovly_mthd,
+                                  disp, 3, oclass, argv, argc, pobject);
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt215.c
deleted file mode 100644 (file)
index c947e1e..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-#include "dmacnv50.h"
-#include "rootnv50.h"
-
-#include <nvif/class.h>
-
-const struct nv50_disp_dmac_oclass
-gt215_disp_ovly_oclass = {
-       .base.oclass = GT214_DISP_OVERLAY_CHANNEL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &nv50_disp_dmac_func,
-       .mthd = &g84_disp_ovly_chan_mthd,
-       .chid = 3,
-};
index d0e554601cc18d2cba7e0140af187e9bb97dfd4c..46f5df0b3a1e28164e759a5d50fd07085222fa74 100644 (file)
  */
 #include "dmacnv50.h"
 #include "head.h"
-#include "rootnv50.h"
 
 #include <core/client.h>
 
-#include <nvif/class.h>
 #include <nvif/cl507e.h>
 #include <nvif/unpack.h>
 
 int
-nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func,
-                  const struct nv50_disp_chan_mthd *mthd,
-                  struct nv50_disp_root *root, int chid,
-                  const struct nvkm_oclass *oclass, void *data, u32 size,
-                  struct nvkm_object **pobject)
+nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *func,
+                   const struct nv50_disp_chan_mthd *mthd,
+                   struct nv50_disp *disp, int chid,
+                   const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                   struct nvkm_object **pobject)
 {
        union {
                struct nv50_disp_overlay_channel_dma_v0 v0;
-       } *args = data;
+       } *args = argv;
        struct nvkm_object *parent = oclass->parent;
-       struct nv50_disp *disp = root->disp;
        int head, ret = -ENOSYS;
        u64 push;
 
-       nvif_ioctl(parent, "create disp overlay channel dma size %d\n", size);
-       if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
+       nvif_ioctl(parent, "create disp overlay channel dma size %d\n", argc);
+       if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
                nvif_ioctl(parent, "create disp overlay channel dma vers %d "
                                   "pushbuf %016llx head %d\n",
                           args->v0.version, args->v0.pushbuf, args->v0.head);
@@ -91,7 +88,7 @@ nv50_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_chan_mthd
-nv50_disp_ovly_chan_mthd = {
+nv50_disp_ovly_mthd = {
        .name = "Overlay",
        .addr = 0x000540,
        .prev = 0x000004,
@@ -101,13 +98,10 @@ nv50_disp_ovly_chan_mthd = {
        }
 };
 
-const struct nv50_disp_dmac_oclass
-nv50_disp_ovly_oclass = {
-       .base.oclass = NV50_DISP_OVERLAY_CHANNEL_DMA,
-       .base.minver = 0,
-       .base.maxver = 0,
-       .ctor = nv50_disp_ovly_new,
-       .func = &nv50_disp_dmac_func,
-       .mthd = &nv50_disp_ovly_chan_mthd,
-       .chid = 3,
-};
+int
+nv50_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
+                  struct nv50_disp *disp, struct nvkm_object **pobject)
+{
+       return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &nv50_disp_ovly_mthd,
+                                  disp, 3, oclass, argv, argc, pobject);
+}
index 36ac0d4237c7aab4c0fac0b689316350ea4e1ad9..ebb0803fd1b61ad6897d8fa03a0919f251f04def 100644 (file)
@@ -31,12 +31,15 @@ g84_disp_root = {
        .dmac = {
                &g84_disp_core_oclass,
                &g84_disp_base_oclass,
-               &g84_disp_ovly_oclass,
        },
        .pioc = {
                &g84_disp_oimm_oclass,
                &g84_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,G82_DISP_OVERLAY_CHANNEL_DMA},  g84_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 18b87b3df862ffedd6e204a2f72b2d5a0d0ba656..6949cf0d9825932fd35891688a345e6b84caad05 100644 (file)
@@ -31,12 +31,15 @@ g94_disp_root = {
        .dmac = {
                &g94_disp_core_oclass,
                &gt200_disp_base_oclass,
-               &gt200_disp_ovly_oclass,
        },
        .pioc = {
                &g84_disp_oimm_oclass,
                &g84_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 7c5701f0b496be7ec1b08dbe79543a5add80cbad..acc897f943fc92c9666d90cd146a5db1e5d87f8e 100644 (file)
@@ -31,12 +31,15 @@ gf119_disp_root = {
        .dmac = {
                &gf119_disp_core_oclass,
                &gf119_disp_base_oclass,
-               &gf119_disp_ovly_oclass,
        },
        .pioc = {
                &gf119_disp_oimm_oclass,
                &gf119_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index c0946a602b719ec5a802329519118fee5ae2e5de..2d19a0613a089912b7c52992eb2b4b9a8bbbd260 100644 (file)
@@ -31,12 +31,15 @@ gk104_disp_root = {
        .dmac = {
                &gk104_disp_core_oclass,
                &gk104_disp_base_oclass,
-               &gk104_disp_ovly_oclass,
        },
        .pioc = {
                &gk104_disp_oimm_oclass,
                &gk104_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 2ebc16687b507d80a14f5e8282384b9f0bd0e5f4..d7e224962e146b62d2b9fba7588d950a749f44bc 100644 (file)
@@ -31,12 +31,15 @@ gk110_disp_root = {
        .dmac = {
                &gk110_disp_core_oclass,
                &gk110_disp_base_oclass,
-               &gk104_disp_ovly_oclass,
        },
        .pioc = {
                &gk104_disp_oimm_oclass,
                &gk104_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 5a62c9e1a2cf074c8fdd63cad5caf2d20b24cc19..de87b2743b226b4072db47d65fe53f4a82ba3a06 100644 (file)
@@ -31,12 +31,15 @@ gm107_disp_root = {
        .dmac = {
                &gm107_disp_core_oclass,
                &gk110_disp_base_oclass,
-               &gk104_disp_ovly_oclass,
        },
        .pioc = {
                &gk104_disp_oimm_oclass,
                &gk104_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 2634e06bf6663b629b8243b237994285e7cb9a14..9e97c1e6548e42bc45ecc18a8bd6b46e714c747b 100644 (file)
@@ -31,12 +31,15 @@ gm200_disp_root = {
        .dmac = {
                &gm200_disp_core_oclass,
                &gk110_disp_base_oclass,
-               &gk104_disp_ovly_oclass,
        },
        .pioc = {
                &gk104_disp_oimm_oclass,
                &gk104_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 784723597c7eb2345084f82206f4e2782a223699..af7031ff4085a720fdf491d68b73cdb73064dd9b 100644 (file)
@@ -31,12 +31,15 @@ gp100_disp_root = {
        .dmac = {
                &gp100_disp_core_oclass,
                &gk110_disp_base_oclass,
-               &gk104_disp_ovly_oclass,
        },
        .pioc = {
                &gk104_disp_oimm_oclass,
                &gk104_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 2fdfa8df037820cd2926a95425595dd5d05cb996..7603a4131581f9600443a25d40163dcc5d21d910 100644 (file)
@@ -31,12 +31,15 @@ gp102_disp_root = {
        .dmac = {
                &gp102_disp_core_oclass,
                &gp102_disp_base_oclass,
-               &gp102_disp_ovly_oclass,
        },
        .pioc = {
                &gp102_disp_oimm_oclass,
                &gp102_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index facad2794eb6979cf646448ebce1452c5cb41364..8ef149d954cb26fcdcfcaa9fdef1d53686f3cf11 100644 (file)
@@ -31,12 +31,15 @@ gt200_disp_root = {
        .dmac = {
                &gt200_disp_core_oclass,
                &gt200_disp_base_oclass,
-               &gt200_disp_ovly_oclass,
        },
        .pioc = {
                &g84_disp_oimm_oclass,
                &g84_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 3e93db58263f323c21336bc9f05e58046681172b..07c8013eddb9eaa8bb3e68478e41a61838078454 100644 (file)
@@ -31,12 +31,15 @@ gt215_disp_root = {
        .dmac = {
                &gt215_disp_core_oclass,
                &gt215_disp_base_oclass,
-               &gt215_disp_ovly_oclass,
        },
        .pioc = {
                &gt215_disp_oimm_oclass,
                &gt215_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA},   g84_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 072c8c0e7096046a5717f18990d94fc885f7e49f..f02368ffa1c9323c7d4828a974758493c342edb5 100644 (file)
@@ -288,6 +288,15 @@ nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass,
                            sclass->chid.user, oclass, data, size, pobject);
 }
 
+static int
+nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
+                         void *argv, u32 argc, struct nvkm_object **pobject)
+{
+       struct nv50_disp *disp = nv50_disp_root(oclass->parent)->disp;
+       const struct nv50_disp_user *user = oclass->priv;
+       return user->ctor(oclass, argv, argc, disp, pobject);
+}
+
 static int
 nv50_disp_root_child_get_(struct nvkm_object *object, int index,
                          struct nvkm_oclass *sclass)
@@ -310,6 +319,15 @@ nv50_disp_root_child_get_(struct nvkm_object *object, int index,
                return 0;
        }
 
+       index -= ARRAY_SIZE(root->func->pioc);
+
+       if (root->func->user[index].ctor) {
+               sclass->base = root->func->user[index].base;
+               sclass->priv = root->func->user + index;
+               sclass->ctor = nv50_disp_root_child_new_;
+               return 0;
+       }
+
        return -EINVAL;
 }
 
@@ -351,12 +369,15 @@ nv50_disp_root = {
        .dmac = {
                &nv50_disp_core_oclass,
                &nv50_disp_base_oclass,
-               &nv50_disp_ovly_oclass,
        },
        .pioc = {
                &nv50_disp_oimm_oclass,
                &nv50_disp_curs_oclass,
        },
+       .user = {
+               {{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
+               {}
+       },
 };
 
 static int
index 06b554b212bdfab1b415003a4490e5fcc858fd95..1c4985a059cd297851fe9e46cbab0bef2fb181bf 100644 (file)
@@ -13,8 +13,13 @@ struct nv50_disp_root {
 };
 
 struct nv50_disp_root_func {
-       const struct nv50_disp_dmac_oclass *dmac[3];
+       const struct nv50_disp_dmac_oclass *dmac[2];
        const struct nv50_disp_pioc_oclass *pioc[2];
+       struct nv50_disp_user {
+               struct nvkm_sclass base;
+               int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,
+                           struct nv50_disp *, struct nvkm_object **);
+       } user[];
 };
 
 int  nv50_disp_root_new_(const struct nv50_disp_root_func *, struct nvkm_disp *,