drm/amdgpu: Initialize SPM_VMID with 0xf (v2)

SPM_VMID is a global resource, SPM access the video memory according to
SPM_VMID. The initial valude of SPM_VMID is 0 which is used by kernel.
That means UMD can overwrite the memory of VMID0 by enabling SPM, that
is really dangerous.

Initialize SPM_VMID with 0xf, it messes up other user mode process at
most.

v2: squash in indentation fix

Signed-off-by: Jacob He <jacob.he@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index d3d4707f21688e8a1cba8a6a96390aa4dcfa7b86..52509c254cbd8ac31929b4e0a20731104a885c8d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -126,6 +126,7 @@ struct amdgpu_rlc_funcs {
        void (*stop)(struct amdgpu_device *adev);
        void (*reset)(struct amdgpu_device *adev);
        void (*start)(struct amdgpu_device *adev);
+       void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
 };
 
 struct amdgpu_rlc {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8b17f182d53294d538055c58920821bd0cb2f748..0649472cb1866842c32386072253d2f65869162a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1016,6 +1016,10 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
                        return r;
        }
 
+       /* init spm vmid with 0xf */
+       if (adev->gfx.rlc.funcs->update_spm_vmid)
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+
        return 0;
 }
 
@@ -4209,6 +4213,18 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
        return 0;
 }
 
+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+       u32 data;
+
+       data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+
+       data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
+       data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+
+       WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+}
+
 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
        .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
        .set_safe_mode = gfx_v10_0_set_safe_mode,
@@ -4219,7 +4235,8 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
        .resume = gfx_v10_0_rlc_resume,
        .stop = gfx_v10_0_rlc_stop,
        .reset = gfx_v10_0_rlc_reset,
-       .start = gfx_v10_0_rlc_start
+       .start = gfx_v10_0_rlc_start,
+       .update_spm_vmid = gfx_v10_0_update_spm_vmid
 };
 
 static int gfx_v10_0_set_powergating_state(void *handle,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 172905dadf9a42b663208639882ea0b8f19d8764..733d398c61ccb7b6b94c4b4384f4fd4f6f1d4ddb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3346,6 +3346,10 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
                        return r;
        }
 
+       /* init spm vmid with 0xf */
+       if (adev->gfx.rlc.funcs->update_spm_vmid)
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+
        return 0;
 }
 
@@ -3570,6 +3574,18 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
        return 0;
 }
 
+static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+       u32 data;
+
+       data = RREG32(mmRLC_SPM_VMID);
+
+       data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
+       data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
+
+       WREG32(mmRLC_SPM_VMID, data);
+}
+
 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
 {
        u32 data, orig, tmp, tmp2;
@@ -4221,7 +4237,8 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
        .resume = gfx_v7_0_rlc_resume,
        .stop = gfx_v7_0_rlc_stop,
        .reset = gfx_v7_0_rlc_reset,
-       .start = gfx_v7_0_rlc_start
+       .start = gfx_v7_0_rlc_start,
+       .update_spm_vmid = gfx_v7_0_update_spm_vmid
 };
 
 static int gfx_v7_0_early_init(void *handle)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e63f98b2d38974cdd2fbdd6f9251d92521c4d915..393a1324daa9326d5bf07c69b974c1ba9dd32ff2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1318,6 +1318,10 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
                        return r;
        }
 
+       /* init spm vmid with 0xf */
+       if (adev->gfx.rlc.funcs->update_spm_vmid)
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+
        return 0;
 }
 
@@ -5594,6 +5598,18 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+       u32 data;
+
+       data = RREG32(mmRLC_SPM_VMID);
+
+       data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
+       data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
+
+       WREG32(mmRLC_SPM_VMID, data);
+}
+
 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
        .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
        .set_safe_mode = gfx_v8_0_set_safe_mode,
@@ -5605,7 +5621,8 @@ static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
        .resume = gfx_v8_0_rlc_resume,
        .stop = gfx_v8_0_rlc_stop,
        .reset = gfx_v8_0_rlc_reset,
-       .start = gfx_v8_0_rlc_start
+       .start = gfx_v8_0_rlc_start,
+       .update_spm_vmid = gfx_v8_0_update_spm_vmid
 };
 
 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index aeaee75020157da9e02e2097fbb29427ff209b36..2fcc5daf99fb85b41cd763a1da67b38237e6297b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1847,6 +1847,10 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
                break;
        }
 
+       /* init spm vmid with 0xf */
+       if (adev->gfx.rlc.funcs->update_spm_vmid)
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+
        return 0;
 }
 
@@ -4753,6 +4757,18 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
        return 0;
 }
 
+static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+       u32 data;
+
+       data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+
+       data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
+       data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+
+       WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+}
+
 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
        .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
        .set_safe_mode = gfx_v9_0_set_safe_mode,
@@ -4764,7 +4780,8 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
        .resume = gfx_v9_0_rlc_resume,
        .stop = gfx_v9_0_rlc_stop,
        .reset = gfx_v9_0_rlc_reset,
-       .start = gfx_v9_0_rlc_start
+       .start = gfx_v9_0_rlc_start,
+       .update_spm_vmid = gfx_v9_0_update_spm_vmid
 };
 
 static int gfx_v9_0_set_powergating_state(void *handle,