drm/amd/display: fix re-enabling stutter for raven

We were overwriting the whole register which was re-enabling
stutter for raven. Now we are reading the register then setting
the values only for pstate.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 0a058e0c3fec846068026d20545d0019623cb0b5..9a04b8758888da9df3ffff9c50b0358bc4684263 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -446,6 +446,8 @@ struct dce_hwseq_registers {
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
+       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
+       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
        HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
@@ -554,6 +556,8 @@ struct dce_hwseq_registers {
        type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
        type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
        type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
+       type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
+       type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
        type DCHUBBUB_ARB_SAT_LEVEL;\
        type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
        type OPP_PIPE_CLOCK_EN;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 072c48188b793e5cfe032a07e9a65cc7e00d45f1..db774b3c3721becac2a80fef3989cc0338773766 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -253,7 +253,6 @@ static void verify_allow_pstate_change_high(
 
        unsigned int debug_index = 0x7;
        unsigned int debug_data;
-       unsigned int force_allow_pstate = 0x30;
        unsigned int i;
 
        if (forced_pstate_allow) {
@@ -261,7 +260,9 @@ static void verify_allow_pstate_change_high(
                 * we verify_allow_pstate_change_high.  so disable force
                 * here so we can check status
                 */
-               REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, 0);
+               REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                            DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
+                            DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
                forced_pstate_allow = false;
        }
 
@@ -304,7 +305,9 @@ static void verify_allow_pstate_change_high(
        /* force pstate allow to prevent system hang
         * and break to debugger to investigate
         */
-       REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
+       REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                    DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
+                    DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
        forced_pstate_allow = true;
 
        if (should_log_hw_state) {