x86: minnowmax: Remove smsc47x superio codes
authorBin Meng <bmeng.cn@gmail.com>
Thu, 30 Jul 2015 10:49:14 +0000 (03:49 -0700)
committerSimon Glass <sjg@chromium.org>
Wed, 5 Aug 2015 14:42:39 +0000 (08:42 -0600)
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
board/intel/minnowmax/minnowmax.c
include/configs/minnowmax.h

index 383cae068bdff48b828c4b137fd96fae9e5d1d4e..c4f2c33b877f8b1ead8753a089ed14ad0cbfad1e 100644 (file)
@@ -6,12 +6,7 @@
 
 #include <common.h>
 #include <asm/gpio.h>
-#include <asm/ibmpc.h>
-#include <asm/pnp_def.h>
 #include <netdev.h>
-#include <smsc_lpc47m.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, 4)
 
 int arch_early_init_r(void)
 {
@@ -21,13 +16,6 @@ int arch_early_init_r(void)
        return 0;
 }
 
-int board_early_init_f(void)
-{
-       lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
-
-       return 0;
-}
-
 void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
        return;
index 4781e792f9bc899572bd405889381c2d16ef50e7..655ce3d422ef58aacf8eda708f40415bd3059bad 100644 (file)
 #include <configs/x86-common.h>
 
 #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
 
 #define CONFIG_X86_SERIAL
-#define CONFIG_SMSC_LPC47M
 
 #define CONFIG_PCI_MEM_BUS             0xd0000000
 #define CONFIG_PCI_MEM_PHYS            CONFIG_PCI_MEM_BUS