arm926ejs, at91: add common phy_reset function
authorHeiko Schocher <hs@denx.de>
Mon, 18 Nov 2013 07:07:23 +0000 (08:07 +0100)
committerAndreas Bießmann <andreas.devel@googlemail.com>
Sun, 1 Dec 2013 21:38:52 +0000 (22:38 +0100)
add common phy reset code into a common function.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Jens Scharsig <esw@bus-elektronik.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Markus Hubig <mhubig@imko.de>
Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
21 files changed:
arch/arm/cpu/at91-common/Makefile
arch/arm/cpu/at91-common/phy.c [new file with mode: 0644]
arch/arm/include/asm/arch-at91/at91_common.h
board/BuS/vl_ma2sc/vl_ma2sc.c
board/afeb9260/afeb9260.c
board/atmel/at91sam9260ek/at91sam9260ek.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/bluewater/snapper9260/snapper9260.c
board/calao/sbc35_a9g20/sbc35_a9g20.c
board/eukrea/cpu9260/cpu9260.c
board/taskit/stamp9g20/stamp9g20.c
include/configs/afeb9260.h
include/configs/at91sam9260ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/cpu9260.h
include/configs/sbc35_a9g20.h
include/configs/snapper9260.h
include/configs/stamp9g20.h
include/configs/vl_ma2sc.h

index d97053ff0a56a9742969f4f56f17768e4f8a8e41..5b978384ebace2096c2e2c42a6398061a65eae42 100644 (file)
@@ -8,4 +8,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
new file mode 100644 (file)
index 0000000..3b6c60c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+       unsigned long erstl;
+       unsigned long start = get_timer(0);
+       unsigned long const timeout = 1000; /* 1000ms */
+       at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+       /*
+        * Need to reset PHY -> 500ms reset
+        * Reset PHY by pulling the NRST line for 500ms to low. To do so
+        * disable user reset for low level on NRST pin and poll the NRST
+        * level in reset status register.
+        */
+       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+               AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+       /* Wait for end of hardware reset */
+       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+               /* avoid shutdown by watchdog */
+               WATCHDOG_RESET();
+               mdelay(10);
+
+               /* timeout for not getting stuck in an endless loop */
+               if (get_timer(start) >= timeout) {
+                       puts("*** ERROR: Timeout waiting for PHY reset!\n");
+                       break;
+               }
+       };
+
+       /* Restore NRST value */
+       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}
index 3ca4d5b08d7a1c6c5946eb7578ea7f7efccbd03d..59e2f4391c3508000d70b254beae5229a57ff980 100644 (file)
@@ -26,5 +26,6 @@ void at91_plla_init(u32 pllar);
 void at91_mck_init(u32 mckr);
 void at91_pmc_init(void);
 void mem_init(void);
+void at91_phy_reset(void);
 
 #endif /* AT91_COMMON_H */
index e2ae6fde6cbbd0f75bf0f3d2937e87ee1370b230..412ff3b482fd2f5497242b1989d0f320e7cc1781 100644 (file)
@@ -16,7 +16,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91_common.h>
@@ -76,25 +75,12 @@ static void vl_ma2sc_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void vl_ma2sc_macb_hw_init(void)
 {
-       unsigned long   erstl;
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
-       at91_rstc_t     *rstc   = (at91_rstc_t *) ATMEL_BASE_RSTC;
+
        /* Enable clock */
        writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+       at91_phy_reset();
 
        at91_macb_hw_init();
 }
index e1b1c10d52730ce4b6c5e73e1e0a864bc9ca7fbe..ea9575d4138655f49177415a4552c595308825c7 100644 (file)
@@ -13,7 +13,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
@@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
 
        /* Enable EMAC clock */
@@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA28),
               &pioa->pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-               &rstc->mr);
-
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
index 263de49c769deab116692ab59c1e46ab63ba7287..7f14af10112c2df0ea2d222c6d783bb5263a5784 100644 (file)
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <atmel_mci.h>
 
@@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
        /* Enable EMAC clock */
        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void)
                pin_to_mask(AT91_PIN_PA28),
                &pioa->pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-               &rstc->mr);
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
index 2e9246f31ccef49127c332e0d7d2f0902eae4aa4..d42a1730cc38fe338f70526190dda0ad71349d00 100644 (file)
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
@@ -82,10 +81,9 @@ static void at91sam9263ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
-       unsigned long   erstl;
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
        at91_pio_t      *pio    = (at91_pio_t *) ATMEL_BASE_PIO;
-       at91_rstc_t     *rstc   = (at91_rstc_t *) ATMEL_BASE_RSTC;
+
        /* Enable clock */
        writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
@@ -97,23 +95,10 @@ static void at91sam9263ek_macb_hw_init(void)
         *
         * PHY has internal pull-down
         */
-
        writel(1 << 25, &pio->pioc.pudr);
        writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(1 << 25, &pio->pioc.puer);
index 6a071f6b7d5800b8e5c1b9eedd9645178a860d15..b7e2efd2fce14bee705c3630ba9ee1a1347f1407 100644 (file)
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
@@ -88,8 +87,6 @@ static void at91sam9m10g45ek_macb_hw_init(void)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
        /* Enable clock */
        writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
@@ -107,21 +104,7 @@ static void at91sam9m10g45ek_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA13),
               &pioa->pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-               &rstc->mr);
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA15) |
index 8a6919dbb1312c09a1f29f62f5ba57a666e3c54d..bfde1291a59c8138740a76ae2c6b21e949b6a23e 100644 (file)
@@ -14,7 +14,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <net.h>
 #include <netdev.h>
@@ -31,8 +30,6 @@ static void macb_hw_init(void)
 {
        struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
        /* Enable clock */
        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -54,18 +51,7 @@ static void macb_hw_init(void)
        /* Enable ethernet power */
        pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
 
-       /* Need to reset PHY -> 500ms reset */
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-              AT91_RSTC_MR_URSTEN, &rstc->mr);
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+       at91_phy_reset();
 
        /* Bring the ethernet out of reset */
        pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
index ecf261c1aec654a3f68128c69e491b0aad7f7818..2074a93a12cada51529e072aa8ceaf9c16017630 100644 (file)
@@ -15,7 +15,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
        /* Enable EMAC clock */
        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA28),
               &pioa->pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-               &rstc->mr);
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
index 5e1524e07bbe0e9fbd30632844c8c9bac4731397..274f72d427416e77cfe3dfc44ab09a7c03253edb 100644 (file)
@@ -17,7 +17,6 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
@@ -89,29 +88,14 @@ static void cpu9260_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void cpu9260_macb_hw_init(void)
 {
-       unsigned long rstcmr;
        at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-       at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
 
        /* Enable clock */
        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
        at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
 
-       rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
-                               AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end hardware reset */
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-               ;
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
+       at91_phy_reset();
 
        at91_macb_hw_init();
 }
index 704a63bad88a258628e8abf46fa3c11d291e6f00..27cdf77f01213de343d6b1bdd76215add43b34a9 100644 (file)
@@ -19,7 +19,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <watchdog.h>
 
@@ -67,8 +66,6 @@ static void stamp9G20_nand_hw_init(void)
 static void stamp9G20_macb_hw_init(void)
 {
        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-       unsigned long erstl;
 
        /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
        at91_set_gpio_output(AT91_PIN_PA26, 0);
@@ -91,33 +88,7 @@ static void stamp9G20_macb_hw_init(void)
                pin_to_mask(AT91_PIN_PA28),
                &pioa->pudr);
 
-       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-       /* Need to reset PHY -> 500ms reset */
-       writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
-                               ~AT91_RSTC_MR_URSTEN), &rstc->mr);
-       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-       /* Wait for end of hardware reset */
-       unsigned long start = get_timer(0);
-       unsigned long timeout = 1000; /* 1000ms */
-
-       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
-
-               /* avoid shutdown by watchdog */
-               WATCHDOG_RESET();
-               mdelay(10);
-
-               /* timeout for not getting stuck in an endless loop */
-               if (get_timer(start) >= timeout) {
-                       puts("*** ERROR: Timeout waiting for PHY reset!\n");
-                       break;
-               };
-       };
-
-       /* Restore NRST value */
-       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-               &rstc->mr);
+       at91_phy_reset();
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
index 5e718980fff4db6273dd82b51eb1e0eb5b7d9b0d..14bac155a355e1570032ae7dedd8bc714a615306 100644 (file)
 /* Ethernet */
 #define CONFIG_MACB
 #define CONFIG_RESET_PHY_R
-
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_NET_RETRY_COUNT         20
 
 /* USB */
index 1c4bb812f07f9f74105cb936c294d7461a2ac8ef..73917b0ec17b878c4f46dc488b36e4cf06a038cb 100644 (file)
 #define CONFIG_RMII                    1
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R             1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
index 0a1969df98e5cbb30712dfa9d5a16f599cae1f39..b9aa03603968d0a3e71cd49de0d3c8cf56887f8a 100644 (file)
 #define CONFIG_RMII                    1
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R             1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
index 395d44e4a80b50225b34c56e120864f9ef75251b..0a4c781d3d468ebe25ce5d2fffb7faebab8194c0 100644 (file)
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_EHCI
index ccf36a5f93847abb1de613fcd77386d88b158972..22c0a0915c1adaf5a05462bb1fd643a4015c69f0 100644 (file)
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT                 20
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* LEDS */
 /* Status LED */
index cbcd4e16b2cf869808ebffd9d63fb271ef997503..7e16c451c378710b3cd4ff6623cd6a1783b9c817 100644 (file)
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
index 7ef51251636de9bf7946756fc8d7d6bd7f8bb9f5..94a65c4d01c84c36586da6e8bbd65fcaae7053d1 100644 (file)
@@ -59,6 +59,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT         20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_TFTP_PORT
 #define CONFIG_TFTP_TSIZE
 
index 248e657e4cf3e709b66c13b8bbc0489f2f052b9a..51339b1496e6180465ce9911da0366b4703ed88e 100644 (file)
 #ifdef CONFIG_MACB
 # define CONFIG_RMII                   /* use reduced MII inteface */
 # define CONFIG_NET_RETRY_COUNT        20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* BOOTP and DHCP options */
 # define CONFIG_BOOTP_BOOTFILESIZE
index 14890800413e9263f2faad1f34f76f84e141ffea..aacb84c8b5ea1500c7e5e4c4a2aac990493cbce4 100644 (file)
 #define CONFIG_RMII
 #define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT         5
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE