.ops = &clk_rcg2_ops,
},
};
-@@ -975,6 +647,18 @@ static const struct freq_tbl ftbl_pcie_a
- F(19200000, P_XO, 1, 0, 0),
+@@ -976,6 +648,18 @@ static const struct freq_tbl ftbl_pcie_a
+ { }
};
+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75024,
.freq_tbl = ftbl_pcie_aux_clk_src,
-@@ -983,12 +667,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
+@@ -984,12 +668,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_aux_clk_src",
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
-@@ -997,8 +691,8 @@ static struct clk_regmap_mux pcie0_pipe_
+@@ -998,8 +692,8 @@ static struct clk_regmap_mux pcie0_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie0_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1013,7 +707,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
+@@ -1014,7 +708,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.ops = &clk_rcg2_ops,
},
};
-@@ -1026,12 +720,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
+@@ -1027,12 +721,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_aux_clk_src",
static struct clk_regmap_mux pcie1_pipe_clk_src = {
.reg = 0x7601c,
.shift = 8,
-@@ -1040,8 +744,8 @@ static struct clk_regmap_mux pcie1_pipe_
+@@ -1041,8 +745,8 @@ static struct clk_regmap_mux pcie1_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1060,6 +764,20 @@ static const struct freq_tbl ftbl_sdcc_a
+@@ -1061,6 +765,20 @@ static const struct freq_tbl ftbl_sdcc_a
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
-@@ -1068,8 +786,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
+@@ -1069,8 +787,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.ops = &clk_rcg2_floor_ops,
},
};
-@@ -1080,6 +798,20 @@ static const struct freq_tbl ftbl_sdcc_i
- F(308570000, P_GPLL6, 3.5, 0, 0),
+@@ -1082,6 +800,20 @@ static const struct freq_tbl ftbl_sdcc_i
+ { }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
-@@ -1088,8 +820,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
+@@ -1090,8 +822,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1102,8 +834,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
+@@ -1104,8 +836,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.ops = &clk_rcg2_floor_ops,
},
};
-@@ -1115,6 +847,18 @@ static const struct freq_tbl ftbl_usb_ma
+@@ -1117,6 +849,18 @@ static const struct freq_tbl ftbl_usb_ma
{ }
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_usb_master_clk_src,
-@@ -1123,8 +867,8 @@ static struct clk_rcg2 usb0_master_clk_s
+@@ -1125,8 +869,8 @@ static struct clk_rcg2 usb0_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_master_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1142,8 +886,8 @@ static struct clk_rcg2 usb0_aux_clk_src
+@@ -1144,8 +888,8 @@ static struct clk_rcg2 usb0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_aux_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1155,6 +899,20 @@ static const struct freq_tbl ftbl_usb_mo
+@@ -1157,6 +901,20 @@ static const struct freq_tbl ftbl_usb_mo
{ }
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
-@@ -1163,12 +921,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+@@ -1165,12 +923,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_mock_utmi_clk_src",
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
-@@ -1177,8 +945,8 @@ static struct clk_regmap_mux usb0_pipe_c
+@@ -1179,8 +947,8 @@ static struct clk_regmap_mux usb0_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb0_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1193,8 +961,8 @@ static struct clk_rcg2 usb1_master_clk_s
+@@ -1195,8 +963,8 @@ static struct clk_rcg2 usb1_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_master_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1207,8 +975,8 @@ static struct clk_rcg2 usb1_aux_clk_src
+@@ -1209,8 +977,8 @@ static struct clk_rcg2 usb1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_aux_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1221,12 +989,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+@@ -1223,12 +991,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_mock_utmi_clk_src",
static struct clk_regmap_mux usb1_pipe_clk_src = {
.reg = 0x3f048,
.shift = 8,
-@@ -1235,8 +1013,8 @@ static struct clk_regmap_mux usb1_pipe_c
+@@ -1237,8 +1015,8 @@ static struct clk_regmap_mux usb1_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb1_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1250,8 +1028,9 @@ static struct clk_branch gcc_xo_clk_src
+@@ -1252,8 +1030,9 @@ static struct clk_branch gcc_xo_clk_src
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-@@ -1265,9 +1044,8 @@ static struct clk_fixed_factor gcc_xo_di
+@@ -1267,9 +1046,8 @@ static struct clk_fixed_factor gcc_xo_di
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1285,6 +1063,20 @@ static const struct freq_tbl ftbl_system
+@@ -1287,6 +1065,20 @@ static const struct freq_tbl ftbl_system
{ }
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
-@@ -1292,8 +1084,8 @@ static struct clk_rcg2 system_noc_bfdcd_
+@@ -1294,8 +1086,8 @@ static struct clk_rcg2 system_noc_bfdcd_
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
-@@ -1304,9 +1096,8 @@ static struct clk_fixed_factor system_no
+@@ -1306,9 +1098,8 @@ static struct clk_fixed_factor system_no
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1327,7 +1118,7 @@ static struct clk_rcg2 nss_ce_clk_src =
+@@ -1329,7 +1120,7 @@ static struct clk_rcg2 nss_ce_clk_src =
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ce_clk_src",
.parent_data = gcc_xo_gpll0,
.ops = &clk_rcg2_ops,
},
};
-@@ -1338,6 +1129,20 @@ static const struct freq_tbl ftbl_nss_no
+@@ -1340,6 +1131,20 @@ static const struct freq_tbl ftbl_nss_no
{ }
};
static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
-@@ -1345,8 +1150,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
+@@ -1347,8 +1152,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_noc_bfdcd_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1356,9 +1161,8 @@ static struct clk_fixed_factor nss_noc_c
+@@ -1358,9 +1163,8 @@ static struct clk_fixed_factor nss_noc_c
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "nss_noc_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1371,6 +1175,18 @@ static const struct freq_tbl ftbl_nss_cr
+@@ -1373,6 +1177,18 @@ static const struct freq_tbl ftbl_nss_cr
{ }
};
static struct clk_rcg2 nss_crypto_clk_src = {
.cmd_rcgr = 0x68144,
.freq_tbl = ftbl_nss_crypto_clk_src,
-@@ -1379,8 +1195,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
+@@ -1381,8 +1197,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1394,6 +1210,24 @@ static const struct freq_tbl ftbl_nss_ub
+@@ -1396,6 +1212,24 @@ static const struct freq_tbl ftbl_nss_ub
{ }
};
static struct clk_rcg2 nss_ubi0_clk_src = {
.cmd_rcgr = 0x68104,
.freq_tbl = ftbl_nss_ubi_clk_src,
-@@ -1401,8 +1235,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
+@@ -1403,8 +1237,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1415,9 +1249,8 @@ static struct clk_regmap_div nss_ubi0_di
+@@ -1417,9 +1251,8 @@ static struct clk_regmap_div nss_ubi0_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1432,8 +1265,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
+@@ -1434,8 +1267,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1446,9 +1279,8 @@ static struct clk_regmap_div nss_ubi1_di
+@@ -1448,9 +1281,8 @@ static struct clk_regmap_div nss_ubi1_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1462,6 +1294,16 @@ static const struct freq_tbl ftbl_ubi_mp
+@@ -1464,6 +1296,16 @@ static const struct freq_tbl ftbl_ubi_mp
{ }
};
static struct clk_rcg2 ubi_mpt_clk_src = {
.cmd_rcgr = 0x68090,
.freq_tbl = ftbl_ubi_mpt_clk_src,
-@@ -1469,8 +1311,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
+@@ -1471,8 +1313,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
.parent_map = gcc_xo_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi_mpt_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1481,6 +1323,18 @@ static const struct freq_tbl ftbl_nss_im
+@@ -1483,6 +1325,18 @@ static const struct freq_tbl ftbl_nss_im
{ }
};
static struct clk_rcg2 nss_imem_clk_src = {
.cmd_rcgr = 0x68158,
.freq_tbl = ftbl_nss_imem_clk_src,
-@@ -1488,8 +1342,8 @@ static struct clk_rcg2 nss_imem_clk_src
+@@ -1490,8 +1344,8 @@ static struct clk_rcg2 nss_imem_clk_src
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_imem_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1500,6 +1354,24 @@ static const struct freq_tbl ftbl_nss_pp
+@@ -1502,6 +1356,24 @@ static const struct freq_tbl ftbl_nss_pp
{ }
};
static struct clk_rcg2 nss_ppe_clk_src = {
.cmd_rcgr = 0x68080,
.freq_tbl = ftbl_nss_ppe_clk_src,
-@@ -1507,8 +1379,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
+@@ -1509,8 +1381,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ppe_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1518,9 +1390,8 @@ static struct clk_fixed_factor nss_ppe_c
+@@ -1520,9 +1392,8 @@ static struct clk_fixed_factor nss_ppe_c
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "nss_ppe_cdiv_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1534,6 +1405,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1536,6 +1407,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port1_rx_clk_src = {
.cmd_rcgr = 0x68020,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
-@@ -1541,8 +1428,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
+@@ -1543,8 +1430,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1554,9 +1441,8 @@ static struct clk_regmap_div nss_port1_r
+@@ -1556,9 +1443,8 @@ static struct clk_regmap_div nss_port1_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1571,6 +1457,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1573,6 +1459,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port1_tx_clk_src = {
.cmd_rcgr = 0x68028,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
-@@ -1578,8 +1480,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
+@@ -1580,8 +1482,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1591,9 +1493,8 @@ static struct clk_regmap_div nss_port1_t
+@@ -1593,9 +1495,8 @@ static struct clk_regmap_div nss_port1_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1608,8 +1509,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
+@@ -1610,8 +1511,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1621,9 +1522,8 @@ static struct clk_regmap_div nss_port2_r
+@@ -1623,9 +1524,8 @@ static struct clk_regmap_div nss_port2_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1638,8 +1538,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
+@@ -1640,8 +1540,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1651,9 +1551,8 @@ static struct clk_regmap_div nss_port2_t
+@@ -1653,9 +1553,8 @@ static struct clk_regmap_div nss_port2_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1668,8 +1567,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
+@@ -1670,8 +1569,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1681,9 +1580,8 @@ static struct clk_regmap_div nss_port3_r
+@@ -1683,9 +1582,8 @@ static struct clk_regmap_div nss_port3_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1698,8 +1596,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
+@@ -1700,8 +1598,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1711,9 +1609,8 @@ static struct clk_regmap_div nss_port3_t
+@@ -1713,9 +1611,8 @@ static struct clk_regmap_div nss_port3_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1728,8 +1625,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
+@@ -1730,8 +1627,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1741,9 +1638,8 @@ static struct clk_regmap_div nss_port4_r
+@@ -1743,9 +1640,8 @@ static struct clk_regmap_div nss_port4_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1758,8 +1654,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
+@@ -1760,8 +1656,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1771,9 +1667,8 @@ static struct clk_regmap_div nss_port4_t
+@@ -1773,9 +1669,8 @@ static struct clk_regmap_div nss_port4_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1793,6 +1688,27 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1795,6 +1690,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
-@@ -1800,8 +1716,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
+@@ -1802,8 +1718,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1813,9 +1729,8 @@ static struct clk_regmap_div nss_port5_r
+@@ -1815,9 +1731,8 @@ static struct clk_regmap_div nss_port5_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1835,6 +1750,27 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1837,6 +1752,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
-@@ -1842,8 +1778,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
+@@ -1844,8 +1780,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1855,9 +1791,8 @@ static struct clk_regmap_div nss_port5_t
+@@ -1857,9 +1793,8 @@ static struct clk_regmap_div nss_port5_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1877,6 +1812,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1879,6 +1814,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port6_rx_clk_src = {
.cmd_rcgr = 0x68070,
.freq_tbl = ftbl_nss_port6_rx_clk_src,
-@@ -1884,8 +1835,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
+@@ -1886,8 +1837,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1897,9 +1848,8 @@ static struct clk_regmap_div nss_port6_r
+@@ -1899,9 +1850,8 @@ static struct clk_regmap_div nss_port6_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1919,6 +1869,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1921,6 +1871,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port6_tx_clk_src = {
.cmd_rcgr = 0x68078,
.freq_tbl = ftbl_nss_port6_tx_clk_src,
-@@ -1926,8 +1892,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
+@@ -1928,8 +1894,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1939,9 +1905,8 @@ static struct clk_regmap_div nss_port6_t
+@@ -1941,9 +1907,8 @@ static struct clk_regmap_div nss_port6_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1964,8 +1929,8 @@ static struct clk_rcg2 crypto_clk_src =
+@@ -1966,8 +1931,8 @@ static struct clk_rcg2 crypto_clk_src =
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1975,6 +1940,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
+@@ -1977,6 +1942,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
-@@ -1983,8 +1964,8 @@ static struct clk_rcg2 gp1_clk_src = {
+@@ -1985,8 +1966,8 @@ static struct clk_rcg2 gp1_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1997,8 +1978,8 @@ static struct clk_rcg2 gp2_clk_src = {
+@@ -1999,8 +1980,8 @@ static struct clk_rcg2 gp2_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -2011,8 +1992,8 @@ static struct clk_rcg2 gp3_clk_src = {
+@@ -2013,8 +1994,8 @@ static struct clk_rcg2 gp3_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -2024,9 +2005,8 @@ static struct clk_branch gcc_blsp1_ahb_c
+@@ -2026,9 +2007,8 @@ static struct clk_branch gcc_blsp1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2041,9 +2021,8 @@ static struct clk_branch gcc_blsp1_qup1_
+@@ -2043,9 +2023,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2058,9 +2037,8 @@ static struct clk_branch gcc_blsp1_qup1_
+@@ -2060,9 +2039,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2075,9 +2053,8 @@ static struct clk_branch gcc_blsp1_qup2_
+@@ -2077,9 +2055,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2092,9 +2069,8 @@ static struct clk_branch gcc_blsp1_qup2_
+@@ -2094,9 +2071,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2109,9 +2085,8 @@ static struct clk_branch gcc_blsp1_qup3_
+@@ -2111,9 +2087,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2126,9 +2101,8 @@ static struct clk_branch gcc_blsp1_qup3_
+@@ -2128,9 +2103,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2143,9 +2117,8 @@ static struct clk_branch gcc_blsp1_qup4_
+@@ -2145,9 +2119,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2160,9 +2133,8 @@ static struct clk_branch gcc_blsp1_qup4_
+@@ -2162,9 +2135,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2177,9 +2149,8 @@ static struct clk_branch gcc_blsp1_qup5_
+@@ -2179,9 +2151,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2194,9 +2165,8 @@ static struct clk_branch gcc_blsp1_qup5_
+@@ -2196,9 +2167,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2211,9 +2181,8 @@ static struct clk_branch gcc_blsp1_qup6_
+@@ -2213,9 +2183,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2228,9 +2197,8 @@ static struct clk_branch gcc_blsp1_qup6_
+@@ -2230,9 +2199,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2245,9 +2213,8 @@ static struct clk_branch gcc_blsp1_uart1
+@@ -2247,9 +2215,8 @@ static struct clk_branch gcc_blsp1_uart1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2262,9 +2229,8 @@ static struct clk_branch gcc_blsp1_uart2
+@@ -2264,9 +2231,8 @@ static struct clk_branch gcc_blsp1_uart2
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2279,9 +2245,8 @@ static struct clk_branch gcc_blsp1_uart3
+@@ -2281,9 +2247,8 @@ static struct clk_branch gcc_blsp1_uart3
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2296,9 +2261,8 @@ static struct clk_branch gcc_blsp1_uart4
+@@ -2298,9 +2263,8 @@ static struct clk_branch gcc_blsp1_uart4
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2313,9 +2277,8 @@ static struct clk_branch gcc_blsp1_uart5
+@@ -2315,9 +2279,8 @@ static struct clk_branch gcc_blsp1_uart5
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2330,9 +2293,8 @@ static struct clk_branch gcc_blsp1_uart6
+@@ -2332,9 +2295,8 @@ static struct clk_branch gcc_blsp1_uart6
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2348,9 +2310,8 @@ static struct clk_branch gcc_prng_ahb_cl
+@@ -2350,9 +2312,8 @@ static struct clk_branch gcc_prng_ahb_cl
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2365,9 +2326,8 @@ static struct clk_branch gcc_qpic_ahb_cl
+@@ -2367,9 +2328,8 @@ static struct clk_branch gcc_qpic_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2382,9 +2342,8 @@ static struct clk_branch gcc_qpic_clk =
+@@ -2384,9 +2344,8 @@ static struct clk_branch gcc_qpic_clk =
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2399,9 +2358,8 @@ static struct clk_branch gcc_pcie0_ahb_c
+@@ -2401,9 +2360,8 @@ static struct clk_branch gcc_pcie0_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2416,9 +2374,8 @@ static struct clk_branch gcc_pcie0_aux_c
+@@ -2418,9 +2376,8 @@ static struct clk_branch gcc_pcie0_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2433,9 +2390,8 @@ static struct clk_branch gcc_pcie0_axi_m
+@@ -2435,9 +2392,8 @@ static struct clk_branch gcc_pcie0_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_m_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2450,9 +2406,8 @@ static struct clk_branch gcc_pcie0_axi_s
+@@ -2452,9 +2408,8 @@ static struct clk_branch gcc_pcie0_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2468,9 +2423,8 @@ static struct clk_branch gcc_pcie0_pipe_
+@@ -2470,9 +2425,8 @@ static struct clk_branch gcc_pcie0_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2485,9 +2439,8 @@ static struct clk_branch gcc_sys_noc_pci
+@@ -2487,9 +2441,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2502,9 +2455,8 @@ static struct clk_branch gcc_pcie1_ahb_c
+@@ -2504,9 +2457,8 @@ static struct clk_branch gcc_pcie1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2519,9 +2471,8 @@ static struct clk_branch gcc_pcie1_aux_c
+@@ -2521,9 +2473,8 @@ static struct clk_branch gcc_pcie1_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2536,9 +2487,8 @@ static struct clk_branch gcc_pcie1_axi_m
+@@ -2538,9 +2489,8 @@ static struct clk_branch gcc_pcie1_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_m_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2553,9 +2503,8 @@ static struct clk_branch gcc_pcie1_axi_s
+@@ -2555,9 +2505,8 @@ static struct clk_branch gcc_pcie1_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_s_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2571,9 +2520,8 @@ static struct clk_branch gcc_pcie1_pipe_
+@@ -2573,9 +2522,8 @@ static struct clk_branch gcc_pcie1_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2588,9 +2536,8 @@ static struct clk_branch gcc_sys_noc_pci
+@@ -2590,9 +2538,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2605,9 +2552,8 @@ static struct clk_branch gcc_usb0_aux_cl
+@@ -2607,9 +2554,8 @@ static struct clk_branch gcc_usb0_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2622,9 +2568,8 @@ static struct clk_branch gcc_sys_noc_usb
+@@ -2624,9 +2570,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2639,9 +2584,8 @@ static struct clk_branch gcc_usb0_master
+@@ -2641,9 +2586,8 @@ static struct clk_branch gcc_usb0_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_master_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2656,9 +2600,8 @@ static struct clk_branch gcc_usb0_mock_u
+@@ -2658,9 +2602,8 @@ static struct clk_branch gcc_usb0_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_mock_utmi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2673,9 +2616,8 @@ static struct clk_branch gcc_usb0_phy_cf
+@@ -2675,9 +2618,8 @@ static struct clk_branch gcc_usb0_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_phy_cfg_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2691,9 +2633,8 @@ static struct clk_branch gcc_usb0_pipe_c
+@@ -2693,9 +2635,8 @@ static struct clk_branch gcc_usb0_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2708,9 +2649,8 @@ static struct clk_branch gcc_usb0_sleep_
+@@ -2710,9 +2651,8 @@ static struct clk_branch gcc_usb0_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2725,9 +2665,8 @@ static struct clk_branch gcc_usb1_aux_cl
+@@ -2727,9 +2667,8 @@ static struct clk_branch gcc_usb1_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2742,9 +2681,8 @@ static struct clk_branch gcc_sys_noc_usb
+@@ -2744,9 +2683,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2759,9 +2697,8 @@ static struct clk_branch gcc_usb1_master
+@@ -2761,9 +2699,8 @@ static struct clk_branch gcc_usb1_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_master_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2776,9 +2713,8 @@ static struct clk_branch gcc_usb1_mock_u
+@@ -2778,9 +2715,8 @@ static struct clk_branch gcc_usb1_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_mock_utmi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2793,9 +2729,8 @@ static struct clk_branch gcc_usb1_phy_cf
+@@ -2795,9 +2731,8 @@ static struct clk_branch gcc_usb1_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_phy_cfg_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2811,9 +2746,8 @@ static struct clk_branch gcc_usb1_pipe_c
+@@ -2813,9 +2748,8 @@ static struct clk_branch gcc_usb1_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2828,9 +2762,8 @@ static struct clk_branch gcc_usb1_sleep_
+@@ -2830,9 +2764,8 @@ static struct clk_branch gcc_usb1_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_sleep_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2845,9 +2778,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
+@@ -2847,9 +2780,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2862,9 +2794,8 @@ static struct clk_branch gcc_sdcc1_apps_
+@@ -2864,9 +2796,8 @@ static struct clk_branch gcc_sdcc1_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2879,9 +2810,8 @@ static struct clk_branch gcc_sdcc1_ice_c
+@@ -2881,9 +2812,8 @@ static struct clk_branch gcc_sdcc1_ice_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2896,9 +2826,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
+@@ -2898,9 +2828,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2913,9 +2842,8 @@ static struct clk_branch gcc_sdcc2_apps_
+@@ -2915,9 +2844,8 @@ static struct clk_branch gcc_sdcc2_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2930,9 +2858,8 @@ static struct clk_branch gcc_mem_noc_nss
+@@ -2932,9 +2860,8 @@ static struct clk_branch gcc_mem_noc_nss
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_nss_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2947,9 +2874,8 @@ static struct clk_branch gcc_nss_ce_apb_
+@@ -2949,9 +2876,8 @@ static struct clk_branch gcc_nss_ce_apb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_apb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2964,9 +2890,8 @@ static struct clk_branch gcc_nss_ce_axi_
+@@ -2966,9 +2892,8 @@ static struct clk_branch gcc_nss_ce_axi_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2981,9 +2906,8 @@ static struct clk_branch gcc_nss_cfg_clk
+@@ -2983,9 +2908,8 @@ static struct clk_branch gcc_nss_cfg_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2998,9 +2922,8 @@ static struct clk_branch gcc_nss_crypto_
+@@ -3000,9 +2924,8 @@ static struct clk_branch gcc_nss_crypto_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3015,9 +2938,8 @@ static struct clk_branch gcc_nss_csr_clk
+@@ -3017,9 +2940,8 @@ static struct clk_branch gcc_nss_csr_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_csr_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3032,9 +2954,8 @@ static struct clk_branch gcc_nss_edma_cf
+@@ -3034,9 +2956,8 @@ static struct clk_branch gcc_nss_edma_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3049,9 +2970,8 @@ static struct clk_branch gcc_nss_edma_cl
+@@ -3051,9 +2972,8 @@ static struct clk_branch gcc_nss_edma_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3066,9 +2986,8 @@ static struct clk_branch gcc_nss_imem_cl
+@@ -3068,9 +2988,8 @@ static struct clk_branch gcc_nss_imem_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_imem_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3083,9 +3002,8 @@ static struct clk_branch gcc_nss_noc_clk
+@@ -3085,9 +3004,8 @@ static struct clk_branch gcc_nss_noc_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_noc_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3100,9 +3018,8 @@ static struct clk_branch gcc_nss_ppe_btq
+@@ -3102,9 +3020,8 @@ static struct clk_branch gcc_nss_ppe_btq
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_btq_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3117,9 +3034,8 @@ static struct clk_branch gcc_nss_ppe_cfg
+@@ -3119,9 +3036,8 @@ static struct clk_branch gcc_nss_ppe_cfg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3134,9 +3050,8 @@ static struct clk_branch gcc_nss_ppe_clk
+@@ -3136,9 +3052,8 @@ static struct clk_branch gcc_nss_ppe_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3151,9 +3066,8 @@ static struct clk_branch gcc_nss_ppe_ipe
+@@ -3153,9 +3068,8 @@ static struct clk_branch gcc_nss_ppe_ipe
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_ipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3168,9 +3082,8 @@ static struct clk_branch gcc_nss_ptp_ref
+@@ -3170,9 +3084,8 @@ static struct clk_branch gcc_nss_ptp_ref
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ptp_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3186,9 +3099,8 @@ static struct clk_branch gcc_crypto_ppe_
+@@ -3188,9 +3101,8 @@ static struct clk_branch gcc_crypto_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3203,9 +3115,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+@@ -3205,9 +3117,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_apb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3220,9 +3131,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+@@ -3222,9 +3133,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3237,9 +3147,8 @@ static struct clk_branch gcc_nssnoc_cryp
+@@ -3239,9 +3149,8 @@ static struct clk_branch gcc_nssnoc_cryp
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3254,9 +3163,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+@@ -3256,9 +3165,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3271,9 +3179,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+@@ -3273,9 +3181,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3288,9 +3195,8 @@ static struct clk_branch gcc_nssnoc_qosg
+@@ -3290,9 +3197,8 @@ static struct clk_branch gcc_nssnoc_qosg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_qosgen_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3305,9 +3211,8 @@ static struct clk_branch gcc_nssnoc_snoc
+@@ -3307,9 +3213,8 @@ static struct clk_branch gcc_nssnoc_snoc
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_snoc_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3322,9 +3227,8 @@ static struct clk_branch gcc_nssnoc_time
+@@ -3324,9 +3229,8 @@ static struct clk_branch gcc_nssnoc_time
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_timeout_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3339,9 +3243,8 @@ static struct clk_branch gcc_nssnoc_ubi0
+@@ -3341,9 +3245,8 @@ static struct clk_branch gcc_nssnoc_ubi0
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3356,9 +3259,8 @@ static struct clk_branch gcc_nssnoc_ubi1
+@@ -3358,9 +3261,8 @@ static struct clk_branch gcc_nssnoc_ubi1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3374,9 +3276,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
+@@ -3376,9 +3278,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3392,9 +3293,8 @@ static struct clk_branch gcc_ubi0_axi_cl
+@@ -3394,9 +3295,8 @@ static struct clk_branch gcc_ubi0_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3410,9 +3310,8 @@ static struct clk_branch gcc_ubi0_nc_axi
+@@ -3412,9 +3312,8 @@ static struct clk_branch gcc_ubi0_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_nc_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3428,9 +3327,8 @@ static struct clk_branch gcc_ubi0_core_c
+@@ -3430,9 +3329,8 @@ static struct clk_branch gcc_ubi0_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3446,9 +3344,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
+@@ -3448,9 +3346,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_mpt_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3464,9 +3361,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
+@@ -3466,9 +3363,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3482,9 +3378,8 @@ static struct clk_branch gcc_ubi1_axi_cl
+@@ -3484,9 +3380,8 @@ static struct clk_branch gcc_ubi1_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3500,9 +3395,8 @@ static struct clk_branch gcc_ubi1_nc_axi
+@@ -3502,9 +3397,8 @@ static struct clk_branch gcc_ubi1_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_nc_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3518,9 +3412,8 @@ static struct clk_branch gcc_ubi1_core_c
+@@ -3520,9 +3414,8 @@ static struct clk_branch gcc_ubi1_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3536,9 +3429,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
+@@ -3538,9 +3431,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_mpt_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3553,9 +3445,8 @@ static struct clk_branch gcc_cmn_12gpll_
+@@ -3555,9 +3447,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3570,9 +3461,8 @@ static struct clk_branch gcc_cmn_12gpll_
+@@ -3572,9 +3463,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3587,9 +3477,8 @@ static struct clk_branch gcc_mdio_ahb_cl
+@@ -3589,9 +3479,8 @@ static struct clk_branch gcc_mdio_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdio_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3604,9 +3493,8 @@ static struct clk_branch gcc_uniphy0_ahb
+@@ -3606,9 +3495,8 @@ static struct clk_branch gcc_uniphy0_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3621,9 +3509,8 @@ static struct clk_branch gcc_uniphy0_sys
+@@ -3623,9 +3511,8 @@ static struct clk_branch gcc_uniphy0_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3638,9 +3525,8 @@ static struct clk_branch gcc_uniphy1_ahb
+@@ -3640,9 +3527,8 @@ static struct clk_branch gcc_uniphy1_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3655,9 +3541,8 @@ static struct clk_branch gcc_uniphy1_sys
+@@ -3657,9 +3543,8 @@ static struct clk_branch gcc_uniphy1_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3672,9 +3557,8 @@ static struct clk_branch gcc_uniphy2_ahb
+@@ -3674,9 +3559,8 @@ static struct clk_branch gcc_uniphy2_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3689,9 +3573,8 @@ static struct clk_branch gcc_uniphy2_sys
+@@ -3691,9 +3575,8 @@ static struct clk_branch gcc_uniphy2_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3706,9 +3589,8 @@ static struct clk_branch gcc_nss_port1_r
+@@ -3708,9 +3591,8 @@ static struct clk_branch gcc_nss_port1_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3723,9 +3605,8 @@ static struct clk_branch gcc_nss_port1_t
+@@ -3725,9 +3607,8 @@ static struct clk_branch gcc_nss_port1_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3740,9 +3621,8 @@ static struct clk_branch gcc_nss_port2_r
+@@ -3742,9 +3623,8 @@ static struct clk_branch gcc_nss_port2_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3757,9 +3637,8 @@ static struct clk_branch gcc_nss_port2_t
+@@ -3759,9 +3639,8 @@ static struct clk_branch gcc_nss_port2_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3774,9 +3653,8 @@ static struct clk_branch gcc_nss_port3_r
+@@ -3776,9 +3655,8 @@ static struct clk_branch gcc_nss_port3_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3791,9 +3669,8 @@ static struct clk_branch gcc_nss_port3_t
+@@ -3793,9 +3671,8 @@ static struct clk_branch gcc_nss_port3_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3808,9 +3685,8 @@ static struct clk_branch gcc_nss_port4_r
+@@ -3810,9 +3687,8 @@ static struct clk_branch gcc_nss_port4_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3825,9 +3701,8 @@ static struct clk_branch gcc_nss_port4_t
+@@ -3827,9 +3703,8 @@ static struct clk_branch gcc_nss_port4_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3842,9 +3717,8 @@ static struct clk_branch gcc_nss_port5_r
+@@ -3844,9 +3719,8 @@ static struct clk_branch gcc_nss_port5_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3859,9 +3733,8 @@ static struct clk_branch gcc_nss_port5_t
+@@ -3861,9 +3735,8 @@ static struct clk_branch gcc_nss_port5_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3876,9 +3749,8 @@ static struct clk_branch gcc_nss_port6_r
+@@ -3878,9 +3751,8 @@ static struct clk_branch gcc_nss_port6_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3893,9 +3765,8 @@ static struct clk_branch gcc_nss_port6_t
+@@ -3895,9 +3767,8 @@ static struct clk_branch gcc_nss_port6_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3910,9 +3781,8 @@ static struct clk_branch gcc_port1_mac_c
+@@ -3912,9 +3783,8 @@ static struct clk_branch gcc_port1_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port1_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3927,9 +3797,8 @@ static struct clk_branch gcc_port2_mac_c
+@@ -3929,9 +3799,8 @@ static struct clk_branch gcc_port2_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port2_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3944,9 +3813,8 @@ static struct clk_branch gcc_port3_mac_c
+@@ -3946,9 +3815,8 @@ static struct clk_branch gcc_port3_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port3_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3961,9 +3829,8 @@ static struct clk_branch gcc_port4_mac_c
+@@ -3963,9 +3831,8 @@ static struct clk_branch gcc_port4_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port4_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3978,9 +3845,8 @@ static struct clk_branch gcc_port5_mac_c
+@@ -3980,9 +3847,8 @@ static struct clk_branch gcc_port5_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port5_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3995,9 +3861,8 @@ static struct clk_branch gcc_port6_mac_c
+@@ -3997,9 +3863,8 @@ static struct clk_branch gcc_port6_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port6_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4012,9 +3877,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4014,9 +3879,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4029,9 +3893,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4031,9 +3895,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4046,9 +3909,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4048,9 +3911,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4063,9 +3925,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4065,9 +3927,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4080,9 +3941,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4082,9 +3943,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4097,9 +3957,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4099,9 +3959,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4114,9 +3973,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4116,9 +3975,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4131,9 +3989,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4133,9 +3991,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4148,9 +4005,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4150,9 +4007,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4165,9 +4021,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4167,9 +4023,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4182,9 +4037,8 @@ static struct clk_branch gcc_uniphy1_por
+@@ -4184,9 +4039,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4199,9 +4053,8 @@ static struct clk_branch gcc_uniphy1_por
+@@ -4201,9 +4055,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4216,9 +4069,8 @@ static struct clk_branch gcc_uniphy2_por
+@@ -4218,9 +4071,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4233,9 +4085,8 @@ static struct clk_branch gcc_uniphy2_por
+@@ -4235,9 +4087,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4251,9 +4102,8 @@ static struct clk_branch gcc_crypto_ahb_
+@@ -4253,9 +4104,8 @@ static struct clk_branch gcc_crypto_ahb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4269,9 +4119,8 @@ static struct clk_branch gcc_crypto_axi_
+@@ -4271,9 +4121,8 @@ static struct clk_branch gcc_crypto_axi_
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4287,9 +4136,8 @@ static struct clk_branch gcc_crypto_clk
+@@ -4289,9 +4138,8 @@ static struct clk_branch gcc_crypto_clk
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4304,9 +4152,8 @@ static struct clk_branch gcc_gp1_clk = {
+@@ -4306,9 +4154,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4321,9 +4168,8 @@ static struct clk_branch gcc_gp2_clk = {
+@@ -4323,9 +4170,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4338,9 +4184,8 @@ static struct clk_branch gcc_gp3_clk = {
+@@ -4340,9 +4186,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4362,7 +4207,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
+@@ -4364,7 +4209,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
projects / openwrt / staging / jow.git / commitdiff