arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
authorAnton Staaf <robotboy@chromium.org>
Mon, 17 Oct 2011 23:46:03 +0000 (16:46 -0700)
committerWolfgang Denk <wd@denx.de>
Sun, 23 Oct 2011 18:50:42 +0000 (20:50 +0200)
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
arch/arm/include/asm/cache.h

index d0518be28cac90da47e0dd89fd28e6419cd6f777..eef6a5a8f23c84722a4c72c1270b9004f5c59283 100644 (file)
@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      64
+#endif
+
 #endif /* _ASM_CACHE_H */