pinctrl: sh-pfc: r8a7792: Add QSPI pin groups
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Fri, 2 Sep 2016 21:50:30 +0000 (00:50 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 12 Sep 2016 08:54:30 +0000 (10:54 +0200)
Add QSPI pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/sh-pfc/pfc-r8a7792.c

index 92c670992b3dce60c14737ab722234e9d5d7b68f..0a3e4e03259bde3332165ebe7ccd984a21e13046 100644 (file)
@@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pins[] = {
 static const unsigned int lbsc_ex_cs5_mux[] = {
        EX_CS5_N_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+       /* SPCLK, SSL */
+       RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+       SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+       /* MOSI_IO0, MISO_IO1 */
+       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int qspi_data2_mux[] = {
+       MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+       /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
+       RCAR_GP_PIN(3, 24),
+};
+static const unsigned int qspi_data4_mux[] = {
+       MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
        /* RX, TX */
@@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(lbsc_ex_cs3),
        SH_PFC_PIN_GROUP(lbsc_ex_cs4),
        SH_PFC_PIN_GROUP(lbsc_ex_cs5),
+       SH_PFC_PIN_GROUP(qspi_ctrl),
+       SH_PFC_PIN_GROUP(qspi_data2),
+       SH_PFC_PIN_GROUP(qspi_data4),
        SH_PFC_PIN_GROUP(scif0_data),
        SH_PFC_PIN_GROUP(scif0_clk),
        SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[] = {
        "lbsc_ex_cs5",
 };
 
+static const char * const qspi_groups[] = {
+       "qspi_ctrl",
+       "qspi_data2",
+       "qspi_data4",
+};
+
 static const char * const scif0_groups[] = {
        "scif0_data",
        "scif0_clk",
@@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(du1),
        SH_PFC_FUNCTION(intc),
        SH_PFC_FUNCTION(lbsc),
+       SH_PFC_FUNCTION(qspi),
        SH_PFC_FUNCTION(scif0),
        SH_PFC_FUNCTION(scif3),
        SH_PFC_FUNCTION(sdhi0),