{ "dma_write_prioq_full" },
{ "rxbds_empty" },
{ "rx_discards" },
- { "mbuf_lwm_thresh_hit" },
{ "rx_errors" },
{ "rx_threshold_hit" },
{ "ring_status_update" },
{ "nic_irqs" },
{ "nic_avoided_irqs" },
- { "nic_tx_threshold_hit" }
+ { "nic_tx_threshold_hit" },
+
+ { "mbuf_lwm_thresh_hit" },
};
#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
ESTAT_ADD(nic_avoided_irqs);
ESTAT_ADD(nic_tx_threshold_hit);
+ ESTAT_ADD(mbuf_lwm_thresh_hit);
+
return estats;
}
tg3_stat64_t dma_write_prioq_full;
tg3_stat64_t rxbds_empty;
tg3_stat64_t rx_discards;
- tg3_stat64_t mbuf_lwm_thresh_hit;
tg3_stat64_t rx_errors;
tg3_stat64_t rx_threshold_hit;
tg3_stat64_t nic_avoided_irqs;
tg3_stat64_t nic_tx_threshold_hit;
- u8 __reserved4[0xb00-0x9c0];
+ /* NOT a part of the hardware statistics block format.
+ * These stats are here as storage for tg3_periodic_fetch_stats().
+ */
+ tg3_stat64_t mbuf_lwm_thresh_hit;
+
+ u8 __reserved4[0xb00-0x9c8];
};
/* 'mapping' is superfluous as the chip does not write into
u64 nic_irqs;
u64 nic_avoided_irqs;
u64 nic_tx_threshold_hit;
+
+ u64 mbuf_lwm_thresh_hit;
};
struct tg3_rx_prodring_set {