/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
#define ARCH_NR_GPIOS (192 + 16)
-/* OS clock tick rate */
-#define CLOCK_TICK_RATE 13300000
-
/* Start of RAM */
#define PHYS_OFFSET SDRAM_BASE_ADDR
#ifndef __ASM_ARCH_MXC_TIMEX_H__
#define __ASM_ARCH_MXC_TIMEX_H__
-#include <mach/hardware.h> /* for CLOCK_TICK_RATE */
+#if defined CONFIG_ARCH_MX1
+#define CLOCK_TICK_RATE 16000000
+#elif defined CONFIG_ARCH_MX2
+#define CLOCK_TICK_RATE 13300000
+#elif defined CONFIG_ARCH_MX3
+#define CLOCK_TICK_RATE 16625000
+#endif
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */