drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx

Print various CP register that have valuable informations regarding
GPU lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 08293f1ba6aaabea3a94cda9c8d810cc15178b7f..14098ace156972761131732a0f3bca6dc34732b0 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2316,6 +2316,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(GRBM_STATUS_SE1));
        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                RREG32(SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        evergreen_mc_stop(rdev, &save);
        if (evergreen_mc_wait_for_idle(rdev)) {
                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
@@ -2353,6 +2361,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(GRBM_STATUS_SE1));
        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                RREG32(SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        evergreen_mc_resume(rdev, &save);
        return 0;
 }

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index b50b15c7049839c0b7a04d2dd33acff9fd19a27a..d3bd098e4e19d453aee64b691e6519a0d8c97066 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -88,6 +88,10 @@
 #define        CONFIG_MEMSIZE                                  0x5428
 
 #define        CP_COHER_BASE                                   0x85F8
+#define        CP_STALLED_STAT1                        0x8674
+#define        CP_STALLED_STAT2                        0x8678
+#define        CP_BUSY_STAT                            0x867C
+#define        CP_STAT                                         0x8680
 #define CP_ME_CNTL                                     0x86D8
 #define                CP_ME_HALT                                      (1 << 28)
 #define                CP_PFP_HALT                                     (1 << 26)

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ddfef8cdd8388ff6f63707d756161eac69c41bd2..9945d86d900153b13210bcc967c594c638213f5c 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1122,6 +1122,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(GRBM_STATUS_SE1));
        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                RREG32(SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
                 RREG32(0x14F8));
        dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
@@ -1170,6 +1178,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(GRBM_STATUS_SE1));
        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
                RREG32(SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        evergreen_mc_resume(rdev, &save);
        return 0;
 }

diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index a0b98066e20796a180f429fce4ef2283e285667e..870db340d37760127e1ebb3314680b4715666789 100644 (file)
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -236,6 +236,10 @@
 #define        CP_SEM_WAIT_TIMER                               0x85BC
 #define        CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 #define        CP_COHER_CNTL2                                  0x85E8
+#define        CP_STALLED_STAT1                        0x8674
+#define        CP_STALLED_STAT2                        0x8678
+#define        CP_BUSY_STAT                            0x867C
+#define        CP_STAT                                         0x8680
 #define CP_ME_CNTL                                     0x86D8
 #define                CP_ME_HALT                                      (1 << 28)
 #define                CP_PFP_HALT                                     (1 << 26)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c5b2e90693627902306fc1529883c6a453409f49..e2dee80e27dc1fa41f917139b8d0172c87a59064 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1289,6 +1289,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(R_008014_GRBM_STATUS2));
        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
                RREG32(R_000E50_SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        rv515_mc_stop(rdev, &save);
        if (r600_mc_wait_for_idle(rdev)) {
                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
@@ -1332,6 +1340,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
                RREG32(R_008014_GRBM_STATUS2));
        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
                RREG32(R_000E50_SRBM_STATUS));
+       dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT1));
+       dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
+               RREG32(CP_STALLED_STAT2));
+       dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
+               RREG32(CP_BUSY_STAT));
+       dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
+               RREG32(CP_STAT));
        rv515_mc_resume(rdev, &save);
        return 0;
 }

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 025fd5b6c08c8c0d68bc93c990586cf2cc2b4689..4b116ae75fc2cedd41b2e446f1a421b7a085d81b 100644 (file)
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -153,6 +153,9 @@
 
 #define        CONFIG_MEMSIZE                                  0x5428
 #define CONFIG_CNTL                                    0x5424
+#define        CP_STALLED_STAT1                        0x8674
+#define        CP_STALLED_STAT2                        0x8678
+#define        CP_BUSY_STAT                            0x867C
 #define        CP_STAT                                         0x8680
 #define        CP_COHER_BASE                                   0x85F8
 #define        CP_DEBUG                                        0xC1FC